Specifications

12 A Minimal PowerPCª Boot Sequence for
Executing Compiled C Program s
Sample Boot Sequence
Each of these options can be conÞgured in order to customize the boot sequence for a particular application.
The conÞgurable boot sequence contains #deÞne statements that can be combined to easily create BAT entry
values. For example, the default entry for the upper instruction BAT 1 speciÞes a 32-Mbyte block size, valid
user mode, valid supervisor mode, with a BEPI of 0x0000_0000. This entry can be formed using the header
Þle deÞne statements as follows: IBAT1U_VAL = (VRAM_BASE | BAT_VALID_USER |
BAT_VALID_SUPERVISOR | BAT_BL_32M). Refer to the source Þle for ppcinit.h at the end of this
document for details.
4.2 General Initialization
Processor initialization in the sample boot sequence follows the steps outlined in Part II, ÒPowerPC
Processor Initialization.Ó One of the most important tasks of the boot code is to set the value of the MSR for
the user program. SpeciÞcally, the MSR is set to enable ßoating-point and machine check exceptions. If the
text section relocates from its load location to an address below 0xFFC0_0000, the exception preÞx is
changed to 0x0000_0000 by setting the MSR[IP] to 0. In addition, data and instruction address translation
must be enabled if the MMU is used. The new MSR value is loaded into machine status save/restore register
1 (SRR1). Upon
rÞ , this value will be copied from SRR1 into the MSR.
The timebase register is initialized to 0x0000_0000 in order to place it in a known state. Also, the machine
status save/restore register 0 (SRR0) is modiÞed to contain the address of the user entry point,
USER_ENTRY, after the relocation. The address in SRR0 is the address of the instruction to be executed
upon an
rÞ instruction.
Additionally, the link register is loaded with an address where execution will resume when the user program
completes. In order to provide timing results for benchmarking, the user program returns to the label
save_timebase when complete. The value of the upper and lower time base registers is stored in memory for
later access. After this operation completes, the code sequence will branch to the invalid op vector at
0xFFF0_0700 to indicate completion. The user should set a breakpoint at this address to determine when
the user program has Þnished.
The caches are invalidated and disabled during the majority of the init sequence. This prevents program data
from being preloaded into the caches, which could unfairly speed up a benchmark. Before branching into
the user program, the boot code enables the L1 caches if ICACHE_ON and DCACHE_ON are set to 1 in
ppcinit.h. If L2CACHE_Enable is set, the L2 cache is enabled as well. Finally, if MMU_ON is set to 1, the
boot sequence initializes the BAT registers and enables address translation.
4.3 EABI Register initialization
In order for a C program compiled with an EABI-compliant compiler to execute properly, registers GPR1,
GPR2, and GPR13 must be initialized as described in Part III, ÒPowerPC EABI Compliance.Ó GPR1 should
be loaded with STACK_LOC, the location of the stack reserved for the user program deÞned in ppcinit.h.
Care should be taken to ensure that the stack size is sufÞcient and that it does not grow down into the text,
data, or bss sections of the program during execution.
In the EABI, GPR2 is used to hold the base of the read-only small data area. It is loaded with the value
_SDA2_BASE generated during linking. Similarly, GPR13 holds the small data area base and is loaded with
the symbol _SDA_BASE, also generated by the linker.
The EABI registers GPR2 and GPR13 are initialized by a function called __eabi(). The call to __eabi() is
automatically inserted at the beginning of main() by the compiler. It should not be called directly by the user
program unless the user does not have a main() function. Programs that lack a main() should call __eabi()
before executing any user code. GPR1 is set up by the boot sequence before entry into main().