Specifications

6
Emulation Probe and
Module Target Connection
Information
A 16-pin male 2X8 header Berg
style connector is needed on the
target development board to
connect the PowerPC 603/e/ei
microprocessor interface assembly
to the JTAG debug port of the
microprocessor.
The header should be placed as
close as possible to the processor
to ensure signal integrity. TD0,
TD1, TCK, TMS, and /TRST signal
traces between the JTAG connector
and the PowerPC 603/e/ei must be
less than three inches. If these sig-
nals are connected to other nodes,
you must connect in a daisy chain
between the JTAG debug
connector and the PowerPC
603/e/ei. These signals are sensitive
to crosstalk and cannot be routed
next to active signals, such as clock
lines on the target board.
TD0 1
TDI
NC
TCK
TMS
SRESET
HRESET
CHECKSTOP 15
2 NC
TRST
+3.3V
NC
NC
NC
NC
16 GND
0.1"
Key
0.1"
Figure 4: Target Development Board Header Connector (Top View)
Header PPC 600 Board
Pin No. I/O 600 Resistor
1 Out TD0
2NC
3 In TDI 1KΩ pulldown
4 In TRST 10KΩ pullup
5NC
6 Power* 1KΩ series
7 In TCK 10KΩ pullup
8NC
9 In TMS 10KΩ pullup
10 NC
11 In SRESET 10KΩ pullup
12 NC
13 In HRESET 10KΩ pullup
14 KEY
15 Out CHECKSTOP 1KΩ pullup
16 GND
Table 3. JTAG Interface Connections
* The +POWER signal is sourced from the development board and is used
as a reference signal. It should be the power signal supplied to the
processor (either +3.3V or +5V). It does not supply power to the
emulation probe.
Note
NC Refers to No Connect