Specifications

11
Pods Required
Eight, 16-channel logic analyzer
pods are required for inverse
assembly. These eight pods are
connected to four E5346A high-
density termination adapters
included with the analysis probe.
Five of these adapters are included
with the analysis probe. One addi-
tional adapter is included for the
other signals on the processor.
Probe Loading
• 10 pf on all signals
• 100 Kohms on all signals
Logic Analyzers Supported
• Contact your Agilent field engi-
neer for latest logic analyzer
information.
PowerPC 603/603e
Analysis Probe
The analysis probe allows easy
connection of a logic analyzer to
your Motorola/IBM PowerPC
603/603e QFP target system for
real-time analysis. With the analy-
sis probe solution, you don’t need
to design special debug connec-
tors into your target system.
The Motorola/IBM PowerPC
603/603e analysis probe
consists of:
• Analysis probe board
• Inverse assembler and
configuration files
• 240-pin elastomeric probing
solution
• Five Agilent E5346A high-density
termination adapters
• User’s guide
Elastomeric Probing Solution
The elastomeric probing solution
included in the analysis probe
offers an inexpensive, rugged, and
easy-to-use probing solution for
the 240-pin QFP PowerPC
603/603e package. The probes
require a minimal “keep out” area
around the device, as shown in fig-
ure 14.
A retainer is glued to the top of the
device, which ensures a solid con-
nection to each pin of the device.
Five retainers, a locator tool, and
adhesive are included with each
probe adapter.
Additional retainers and locator
tools may be ordered. E5363A option
201 offers a kit of five additional
retainers and adhesive. An addi-
tional locator tool is available as
E5363A option 202.
Modes of Operation
State Modes
In state-per-address or data-cycle
modes, the logic analyzer records
only those states in which one or
more of the strobes AACK,
ARTRY, TA, DRTRY, or TEA are
asserted. This mode filters wait
states and exposes the PowerPC
603/603e/603ei microprocessor’s
decoupled address and data buses.
In state-per-clock mode, address,
data, and status are captured on
each CPU clock. This mode is use-
ful in hardware validation and
analysis during system crashes.
Timing Mode
Timing analysis is supported. All
microprocessor signals are
presented to the logic analyzer
unbuffered.
Figure 8: Analysis Probe for the
PPC 603/603e