Technical information

AN2216/D

2 MC9S12DP256 Software Development Using Metrowerk’s Codewarrior MOTOROLA

In addition to the hardware paging mechanism, the instruction set has been

enhanced with two instructions that allow inter-page function (subroutine) calls.

The CALL instruction is similar to the JSR instruction, however, in addition to

placing the paged window return address on the stack, it also places the current

value of the PPAGE register on the stack before writing the new 8-bit value

supplied by the CALL instruction to the PPAGE register. The RTC instruction is

similar to the RTS instruction except that it is used to terminate functions called

by the CALL instruction. Both the PPAGE register value and the paged window

address are restored from the stack, continuing execution at the restored

address.

The MC9S12DP256 implements 6 bits of the PPAGE register which gives it a

1MB program memory address space that is accessed through the paged

window. The lower 768K portion of the address space, accessed with PPAGE

values $00 through $2F, are reserved for external memory when the part is

operated in expanded mode. The upper 256K of the address space, accessed

with PPAGE values $30 through $3F, is occupied by the on-chip Flash memory

as shown in Figure 1.

Figure 1. MC9S12DP256 Memory Map

$0000

Flash Control Registers

$3E

$3F

16K Paged

Memory

$4000

$8000

$C000

$FFFF

$30 $31 $32 $33 $34 $35 $36 $37 $38 $39 $3A $3B $3C $3D $3E $3F

Block 3 Block 2 Block 1 Block 0

Protected Low Area

0.5K, 1K, 2K, 4K

Protected High Area

2K, 4K, 8K, 16K

$FF00 - $FF0F, Access Key, Protection,