Technical data

RAM - Local RAM Tests

http://www.motorola.com/computer/literature 3-103

PED - Local Parity Memory Error Detection

Command Input

PPCx-Diag>RAM PED

Description

The memory range and address increment is specified by the RAM test

directory configuration parameters. (Refer to

CF - Test Group Configuration

Parameters Editor

in Chapter 2.)

First, each memory location to be tested has the data portion verified by

writing/verifying all zeros, and all ones. Each memory location to be tested

is tested once with parity interrupt disabled, and once with parity interrupt

enabled. Parity checking is enabled, and data is written and verified at the

test location that causes the parity bit to toggle on and off (verifying that

the parity bit of memory is good). Next, data with incorrect parity is written

to the test location. The data is read, and if a parity error exception does

occur, the fault address is compared to the test address. If the addresses are

the same, the test passed and the test location is incremented until the end

of the test range has been reached.

Response/Messages

After the command has been issued, the following line is printed:

RAM PED: Local Parity Memory Detection.....Running --->

If the board under test does not support Parity error detection, the test is

bypassed:

RAM PED: Local Parity Memory Detection....Running --> BYPASS

If all parts of the test are completed correctly, then the test passes:

RAM PED: Local Parity Memory Detection.....Running ---> PASSED

If any part of the test fails, then the display appears as follows:

RAM PED: Local Parity Memory Detection...... Running ---> FAILED

RAM/PED Test Failure Data:

(error message)