Technical data

3-98 Computer Group Literature Center Web Site
Test Descriptions
3
BTOG - Bit Toggle
Command Input
PPCx-Diag>ram btog
Description
The memory range is specified by the RAM test directory configuration
parameters. (Refer to CF - Test Group Configuration Parameters Editor
in Chapter 2.) The RAM test directory configuration parameters also
determine the value of the global random data seed used by this test. The
global random data seed is incremented after it is used by this test. This test
uses the following test data pattern generation algorithm:
1. Random data seed is copied into a work register.
2. Work register data is shifted right one bit position.
3. Random data seed is added to work register using unsigned
arithmetic.
4. Data in the work register may or may not be complemented.
5. Data in the work register is written to current memory location.
If the RAM test directory configuration parameter for code cache enable
equals “Y”, the microprocessor code cache is enabled. This test is coded to
operate using the 32-bit data size only. Each memory location in the
specified memory range is written with the test data pattern. Each memory
location in the specified memory range is then written with the test data
pattern complemented before it is written. The memory under test is read
back to verify that the complement test data is properly retained. Each
memory location in the specified memory range is then written with the
test data pattern. The memory under test is read back to verify that the test
data is properly retained.