Technical data

3-70 Computer Group Literature Center Web Site
Test Descriptions
3
DFIFO - DMA FIFO
Command Input
PPCx-Diag>NCR DFIFO
Description
This procedure tests the basic ability to write data into the DMA FIFO and
retrieve it in the same order as written. The DMA FIFO is checked for an
empty condition following a software reset, then the FBL2 bit is set and
verified. The FIFO is then filled with 16 bytes of data in the four byte lanes
verifying the byte lane full or empty with each write. Next the FIFO is read
verifying the data and the byte lane full or empty with each read.
If no errors are detected, the NCR device is reset; otherwise the device is
left in the test state.
Response/Messages
After the command has been issued, the following line is printed:
NCR DFIFO: DMA FIFO......................... Running --->
If all parts of the test are completed correctly, then the test passes:
NCR DFIFO: DMA FIFO......................... Running ---> PASSED
If any part of the test fails, then the display appears as follows:
NCR DFIFO: DMA FIFO......................... Running ---> FAILED
NCR/DFIFO Test Failure Data:
(error message)
Here (error message) is one of the following:
DMA FIFO is not initially empty
DMA FIFO Byte Control not enabled
Address =________, Expected =__, Actual =__
DMA FIFO Byte Control Error:
Address =________, Expected =__, Actual =__
DMA FIFO Empty/Full Error:
Address =________, Expected =__, Actual =__