PPCBug Diagnostics Users Manual PPCDIAA/UM3 November 2000 Edition
Notice While reasonable efforts have been made to assure the accuracy of this document, Motorola, Inc. assumes no liability resulting from any omissions in this document, or from the use of the information obtained therein. Motorola reserves the right to revise this document and to make changes from time to time in the content hereof without obligation of Motorola to notify any person of such revision or changes.
Preface The PPCBug Diagnostics Manual provides general information, installation procedures, and a diagnostic firmware guide for the PPCBug Debugging Package. All information contained herein is specific to Motorola’s PowerPC™-based boards. In this manual, they are collectively referred to as the PowerPC board or board. When necessary to refer to them individually, they are identified by their respective models, such as MVME210x, MVME240x, MVME510x, MCP750, and MTX.
Conventions Used in This Manual The following typographical conventions are used in this document: bold is used for user input that you type just as it appears; it is also used for commands, options and arguments to commands, and names of programs, directories and files. italic is used for names of variables to which you assign values. Italic is also used for comments in screen displays and examples, and to introduce new terms.
Motorola® and the Motorola symbol are registered trademarks of Motorola, Inc. PowerStackTM is a trademark of Motorola, Inc. PowerPCTM, and PowerPC 750TM are trademarks of IBM Corp, and are used by Motorola, Inc. under license from IBM Corp. AIXTM is a trademark of IBM Corp. All other products mentioned in this document are trademarks or registered trademarks of their respective holders.
Contents CHAPTER 1 General Information Introduction................................................................................................................1-1 Overview of PPCBug Firmware ................................................................................1-1 Debugger and Diagnostic Directories ........................................................................1-2 Command Entry .........................................................................................................
DEC - Ethernet Controller Tests................................................................................ 3-4 CINIT - Chip Initialization................................................................................. 3-6 CLOAD - Continuous Load ............................................................................... 3-7 CNCTR - Connector........................................................................................... 3-8 ERREN - PERREN/SERREN Bit Toggle..............................
PATTERN - WriteThru Pattern.........................................................................3-58 SIZE - Verify Cache Size..................................................................................3-59 WBFL - Write Back w/Flush ............................................................................3-60 WBINV - Write Back w/Invalidate ..................................................................3-61 WRTHRU - WriteThru ...................................................................
CLK - Real Time Clock Function .................................................................. 3-114 RAM - Battery Backed-Up RAM .................................................................. 3-116 WATCHDOG - Watchdog Time-Out Reset.................................................... 3-117 SCC - Serial Communication Controller (Z85230) Tests ..................................... 3-118 ACCESS - Device/Register Access ...............................................................
List of Figures Figure 2-1. Help Screen (Sheet 1 of 2) ......................................................................
xii
List of Tables Table 2-1. Diagnostic Utilities ...................................................................................2-1 Table 3-1. Diagnostic Test Groups.............................................................................3-1 Table 3-2. CL1283 Test Group ..................................................................................3-2 Table 3-3. DEC Test Group........................................................................................3-4 Table 3-4. DEC Error Messages ..
xiv
1General Information 1 Introduction This manual describes the complete set of hardware diagnostics included in the PPCBug Debugging Package, intended for testing and troubleshooting Motorola’s PowerPC-based boards. This member of the PPCBug firmware family, known as PPCBug diagnostics, is implemented on many of the Motorola PowerPC-based products as part of a standard proprietary debugging and diagnostic tool set. Boards using this tool set are referred to in this manual as the PowerPC board or board.
1 General Information contains a battery of utilities and tests for exercise, test, and debug of hardware in the PowerPC board environment. The diagnostics are menu-driven for ease of use. ❏ A user interface or debug/diagnostics monitor that accepts commands from the system console terminal. The tests described in this manual are implemented by the firmware, commands are input, and results are reported via this monitor, which is the common device used for both the debugger and the diagnostics.
Command Entry Because PPCBug is command-driven, it performs various operations in response to commands that are entered at the keyboard. PPCBug executes the command and the prompt reappears. However, a command is entered that causes execution of some user target code (e.g., GO), then control may or may not return to PPCBug, depending on the outcome of the user program. The Help (HE) command displays a menu of all available diagnostic functions; i.e., the tests and utilities.
1 General Information causes a help screen to appear that gives information about the ERREN test in the DEC test group. Root-Level Command (Test Group): Entering just the name of a test group causes all individual tests that are part of that group to execute in sequence (with some exceptions). For example: PPCx-Diag>RAM causes all Random Access Memory (RAM) tests to execute, except for two that only execute if specified.
Command Entry Multiple Root-Level Commands (Test Groups): Multiple commands may be entered. If a command expects parameters and another command is to follow it, separate the two with a semicolon (;). For example, to invoke the command RTC CLK (to execute the Real Time Clock Function test from the MK48Txx Real Time Clock test group) after the command RAM ADR, the command line would read: PPCx-Diag>RAM ADR; RTC CLK Spaces are not required before or after the semicolon but are shown here for legibility.
1 General Information Installation, Configuration, and Start-Up The PPCBug firmware is installed by Motorola at the factory when your PowerPC board is manufactured. Refer to your PowerPC board installation manual and ensure that all necessary hardware preparation, board installation, connection of peripherals, and hardware configuration, including console selection and configuration of Software Readable Headers (where applicable), has been correctly done.
2Diagnostic Utilities 2 Introduction This chapter contains descriptions and examples of the various diagnostic utilities available in PPCBug. Utilities In addition to individual or sets of tests, the diagnostic package supports the utilities (root-level commands or general commands) listed in the table below and described on the following pages. Table 2-1.
Diagnostic Utilities Table 2-1. Diagnostic Utilities (Continued) 2 Command Description SE Stop-On-Error Mode ST Self Test ZE Clear (Zero) Error Counters ZP Zero Pass Count Notes You may enter command names in either uppercase or lowercase. Terminate all command lines by pressing the RETURN key. AEM - Append Error Messages Mode The AEM command allows you to accumulate error messages in the internal error message buffer of the diagnostic monitor.
Utilities CEM - Clear Error Messages 2 This command allows you to clear the internal error message buffer of the diagnostic monitor manually. Example: PPCx-Diag>cem (error message buffer is cleared) PPCx-Diag> CF - Test Group Configuration Parameters Editor The CF parameters control the operation of all tests in a test group. For example, the RAM test group has parameters such as starting address, ending address, parity enable, etc.
Diagnostic Utilities PPC1-Diag>cf RAM Configuration Data: Starting/Ending Address Enable [Y/N] =N ?RETURN Starting Address =00004000 ?RETURN Ending Address =00F84FFC ?RETURN Random Data Seed =12301983 ?RETURN March Address Pattern =00000000 ?RETURN Instruction (Code) Cache Enable [Y/N] =Y ? .
Utilities DP - Display Pass Count 2 A count of the number of passes in Loop-Continue (LC) mode is kept by the monitor. This count is displayed with other information at the conclusion of each pass. To display this information without using LC, enter DP. Example: PPCx-Diag>dp Pass Count =19 PPCx-Diag> HE - Help The Help command provides on-line documentation.
Diagnostic Utilities 2 PPC1-Diag>he AEM Append Error Messages Mode CEM Clear Error Messages CF Configuration Editor CL1283 Parallel Interface (CL1283) Tests (DIR) CS4231 cs4231 Audio Codec (DIR) DE Display Errors DEC Ethernet Controller (DEC21x40) Tests (DIR) DEM Display Error Messages DP Display Pass Count EIDE EIDE Tests (DIR) HE Help on Tests/Commands HEX Help Extended ISABRDGE ISA Bridge Tests (DIR) KBD8730X Keyboard/Mouse Controller Tests (DIR) L2CACHE L2-Cache (DIR) LA Loop Always Mode LC Loop Contin
Utilities 2 QST Quick Self Test (DIR) RAM Random Access Memory Tests (DIR) RTC MK48Txx Timekeeping (DIR) SCC Serial Communication Controller(Z85C230)Tests (DIR) SE Stop on Error Mode ST Self Test (DIR) UART Serial Input/Output Tests (DIR) VGA54XX VGA Controller (GD54XX) Tests (DIR) VME2 VME2Chip2 Tests (DIR) Z8536 z8536 Counter/Timer Input/Output Tests (DIR) ZE Zero Errors ZP Zero Pass Count PPC1-Diag> Figure 2-1.
Diagnostic Utilities 2 HEX - Help Extended The HEX command goes into an interactive, continuous mode of the HE command. The prompt displayed for HEX is the question mark (?). You may then type the name of a directory or command. You must type QUIT to exit.
Utilities LC - Loop-Continue Mode 2 To repeat a test or series of tests endlessly, enter the prefix LC. This loop includes everything on the command line. To break the loop, press the BREAK key on the diagnostic video display terminal. Certain tests disable the BREAK key interrupt, so it may become necessary to press the abort or reset switches on the PowerPC board front panel. Example: PPCx-Diag>lc;ram adr RAM ADR: Addressability.................
Diagnostic Utilities PPCx-Diag>le;scc SCC ACCESS: Device/Register Access...... Running ---> PASSED SCC IRQ: Interrupt Request.............. Running ---> FAILED 2 SCC/IRQ Test Failure Data: (error message) SCC IRQ: Interrupt Request.............. Running ---> FAILED SCC/IRQ Test Failure Data: (error message) SCC IRQ: Interrupt Request..............
Utilities The LN command has no effect until a test failure occurs, at which time, if the LN command has been previously encountered in the user command line, further printing of the test title and pass/fail status is suppressed. This is useful for more rapid execution of the failing test; i.e., the LN command contributes to a “tighter” loop. Example: PPC1-Diag>LN;RAM ADR RAM ADR: RAM ADR: Addressability........ Running ---> Pass Count =1, Errors This Pass =0, Total Errors =0 RAM ADR: Addressability.......
Diagnostic Utilities PPC1-Diag>mask ram adr Update Non-Volatile RAM (Y/N)? y RAM/ADR PPC1-Diag>mask RAM/ADR PPC1-Diag> 2 NV - Non-Verbose Mode Upon detecting an error, the tests display a substantial amount of data. To avoid the necessity of watching the scrolling display, you can choose a mode that suppresses all messages except test name and PASSED or FAILED. This mode is called non-verbose and you can invoke it prior to calling a command by entering NV.
Utilities If you are in the diagnostic directory and enter SD, you will return to the debug directory. At this point, only the debug commands for PPC1Bug can be entered. If you are in the debug directory and enter SD, you will return to the diagnostic directory. You may enter either the diagnostic or debug commands from the diagnostics directory.
Diagnostic Utilities The commands HE ST and HE QST list the top level commands of the self test directory in alphabetical order. Each test for that particular command is listed in the section pertaining to the command. 2 For details on extended self test operation, refer to the PPCBug Firmware Package User’s Manual. Example: PPC1-Diag>qst RAM ADR: Addressability.............. UART REGA: Register Access............... UART IRQ: Interrupt...................... UART BAUD: Baud Rate.....................
Utilities ZE - Clear (Zero) Error Counters 2 The error counters originally come up with the value of zero, but it is occasionally desirable to reset them to zero at a later time. This command resets all of the error counters to zero. Example: PPC1-Diag>ze PPC1-Diag> This clears all error counters. ZP - Zero Pass Count Invoking the ZP command resets the pass counter to zero. This is frequently desirable before typing in a command that invokes the LoopContinue mode.
Diagnostic Utilities 2 2-16 Computer Group Literature Center Web Site
3Test Descriptions 3 Detailed descriptions of PPCBug’s diagnostic tests are presented in this chapter. The test groups are described in the order shown in the following table. Some test groups do not run on all PowerPC boards. The column PowerPC Board lists the boards on which each group of tests will run. Table 3-1.
Test Descriptions Notes 1. You may enter command names in either uppercase or lowercase. 2. Some diagnostics depend on restart defaults that are set up only in a particular restart mode. Refer to the documentation on a particular diagnostic for the correct mode. 3 CL1283 - Parallel Interface Tests This section describes the CL1283 parallel Interface (CL1283) tests. Note These tests apply only to the MTX boards.
CL1283 - Parallel Interface Tests REG - Register Command Input 3 PPCx-Diag>CL1283 REG Description This test verifies that the CL1283 registers can be read and written. Data patterns verify that every read/write bit can be modified. Response/Messages After the command has been issued, the following line is printed: CL1283 REG: cl1283 Register Access...... Running ---> If all parts of the test are completed correctly, then the test passes: CL1283 REG: cl1283 Register Access......
Test Descriptions DEC - Ethernet Controller Tests These sections describe the individual DEC21x4x Ethernet Controller tests. 3 The firmware now provides support for testing of multiple Ethernet controllers within PCI configuration space. This means that the DEC diagnostics can now be run on multiple DEC Controllers. This is “only” true for any firmware supported DEC21x4x Ethernet devices. Examples of where DEC tests run on multiple controllers include: 1.
DEC - Ethernet Controller Tests Table 3-3. DEC Test Group Name Description CINIT Chip Initialization 3 Executed only when specified: CLOAD Continuous Load CNCTR Connector None of these tests need any external hardware hooked up to the Ethernet port, with the exception of the CNCTR test, which needs external loopback “plugs” in the external connector. http://www.motorola.
Test Descriptions CINIT - Chip Initialization Command Input 3 PPCx-Diag>dec cinit Description This test checks the DEC chip initialization sequence for proper operation while using interrupts and reading the initialization blocks and rings structures used for Ethernet communications. Response/Messages After the command has been issued, the following line is printed: DEC CINIT: Chip Initialization:..........
DEC - Ethernet Controller Tests CLOAD - Continuous Load Command Input 3 PPCx-Diag>DEC CLOAD Description This test verifies that a continuous load can be placed on the controller by transmitting/receiving a sequence of packets totalling at least 1 megabyte of throughput, comparing the input data with the output data. Response/Messages After the command has been issued, the following line is printed: DEC CLOAD: Continuous Load:..............
Test Descriptions CNCTR - Connector Command Input PPCx-Diag>dec cnctr 3 Description This test verifies that the data path through the external (AUI or TP (twisted pair)) connection is functional, by transmitting and receiving packets and comparing the data. This test requires the presence of an external loopback “plug” for AUI or TP. Note It is recommended that the board under test not be connected to a live network while this test is running.
DEC - Ethernet Controller Tests ERREN - PERREN/SERREN Bit Toggle Command Input 3 PPCx-Diag>DEC ERREN Description This test toggles the PERREN and SERREN (Address and Data Parity Error status) bits in the command register found in the PCI header address space to verify that this register functions properly. Each bit is toggled (written) and then read to verify that they are indeed toggled.
Test Descriptions ILR - Interrupt Line Register Access Command Input 3 PPCx-Diag>DEC ILR Description This test sends all possible byte patterns (0x00 - 0xFF) to the Interrupt Line register in the PCI register space. It verifies that the register can be read and written for all possible bit combinations. It checks that the byte read is the same as the byte previously written to verify that the register holds data correctly.
DEC - Ethernet Controller Tests IOR - I/O Resource Register Access Command Input 3 PPCx-Diag>dec ior Description This test reads all the I/O resource registers (pointed to by the PCI Base Address register) and all the indexed registers read indirectly through the RAP index register, and CSR/BCR data registers. This test verifies that the registers can be accessed and that the data paths to the device are functioning.
Test Descriptions REGA - PCI Header Register Access Command Input 3 PPCx-Diag>DEC REGA Description This test performs a read test on the Vendor ID and the Device ID registers in the DEC PCI header space and verifies that they contain the correct values. This test verifies that the registers can be accessed and that the data paths to the device are functioning. Response/Messages After the command has been issued, the following line is printed: DEC REGA: PCI Register Access..........
DEC - Ethernet Controller Tests SPACK - Single Packet Send/Receive Command Input 3 PPCx-Diag>DEC SPACK Description This test verifies that the DEC Ethernet Controller can successfully send and receive an Ethernet packet, using interrupts in internal loopback mode. Response/Messages After the command has been issued, the following line is printed: DEC SPACK: Single Packet Xmit/Recv:.....
Test Descriptions XREGA - Extended PCI Register Access Command Input 3 PPCx-Diag>DEC XREGA Description This test performs a read test on all of the registers in the DEC PCI header space and verifies that they contain the correct values. This test verifies that the registers can be accessed and that the data paths to the device are functioning. Response/Messages After the command has been issued, the following line is printed: DEC XREGA:Extended PCI register Access:.
DEC - Ethernet Controller Tests DEC Error Messages The DEC test group error messages generally take the following form: 3 DEC CLOAD: Continuous Load:..........Running ---> FAILED DEC/CLOAD Test Failure Data: Ethernet packet data mismatch: Iter: nnnn Element: nnn Value sent: xxxx Value returned: xxxx The first line of the test failure data identifies what type of failure occurred. The following line provides additional information about the failure. Table 3-4.
Test Descriptions Table 3-4. DEC Error Messages (Continued) 3 Error Message Symptom or Cause Initialization Error: Transmit Descriptor Ring address mismatch Controller not properly storing the address of the Transmit Descriptor ring after initialization. Not enough diagnostics memory to accommodate DEC buffers. There was not enough diagnostics memory space available for use by the Initialization block, Descriptor Rings, and buffers. PCI XXX register contains invalid data.
DEC - Ethernet Controller Tests Table 3-4. DEC Error Messages (Continued) Error Message Symptom or Cause Transmit of Ethernet Packet Failed: Late Collision (LCOL) A Collision occurred after the slot time of the channel had elapsed. Transmit of Ethernet Packet Failed: Too many Retries (RTRY) Transmit failed too many times, indicating a transmission problem over the network.
Test Descriptions Table 3-4. DEC Error Messages (Continued) 3 Error Message Symptom or Cause Time out waiting for Interrupt An expected interrupt, either from Initialization, Transmit or Receive was never received, indicating some other problem has occurred. Memory Error interrupt encountered (MERR) Interrupt that occurs when the controller cannot access the memory bus. Time Out interrupt encountered (BABL) Interrupt indicating that transmitter has taken too long to transmit a frame.
DEC - Ethernet Controller Tests Table 3-4. DEC Error Messages (Continued) Error Message Symptom or Cause Receive interrupt occurred, but no data available. Controller interrupted indicating that data has been received, but the incoming byte count does not reflect this. Received packet is the wrong size. Size of packet is not the same size as it was when it was sent.
Test Descriptions INET - Intel Ethernet Controller Tests These sections describe the individual Intel 82559/ER Ethernet Controller tests. 3 Entering INET without parameters causes all INET tests to run in the order shown in the table below, except as noted. To run an individual test, add that test name to the INET command. The individual tests are described in alphabetical order on the following pages. Table 3-5.
INET - Intel Ethernet Controller Tests Description This test verifies that the Interrupt Line Register of the PCI Header of the device can be programmed to any possible value. Response/Messages After the command has been issued, the following line is printed: INET BINT: Basic Interrupt Testing...Running--> If all parts of the test are completed correctly, the test passes: INET BINT: Basic Interrupt Testing...
Test Descriptions INET EEPT: EEPROM Test.................Running-->FAILED INET/EEPT Test Failure Data: (error message) 3 Refer to the section INET Error Messages for a list of the error messages and their meaning. INST - Internal Self Test Command Input PPCx-Diag>inet inst Description This test configures the device to perform an internal self test and determines whether the device itself detected an error.
INET - Intel Ethernet Controller Tests Description This test verifies that the bits in the MDI Control Register can be set and reset. Response/Messages After the command has been issued, the following line is printed: INET MDIT: MDI Interface Test..........Running--> If all parts of the test are completed correctly, the test passes: INET MDIT: MDI Interface Test........Running-->PASSED If any part of the test fails, the display appears as follows: INET MDIT: MDI Interface Test........
Test Descriptions If any part of the test fails, the display appears as follows: INET MPACK: Multi Pkt Interrupt LB Testing. Running->FAILED INET/MPACK Test Failure Data: (error message) 3 Refer to the section INET Error Messages for a list of the error messages and their meaning.
INET - Intel Ethernet Controller Tests SERT - SERR# Enable Response Test Command Input 3 PPCx-Diag>inet sert Description This test toggles the SERR (System Enable Response) bit in the command register found in the PCI header address space to verify that this register functions properly. The bit is toggled (written) and then read to verify that it is indeed toggled. Response/Messages After the command has been issued, the following line is printed: INET SERT: SERR# Enable Response Test...
Test Descriptions Response/Messages After the command is issued, the following line is printed: INET SPACK: Single Pkt Interrupt LB Testing. Running--> 3 If all parts of the test are completed correctly, the test passes: INET SPACK: Single Pkt Interrupt LB Testing. Running->PASSED If any part of the test fails, the display appears as follows: INET SPACK: Single Pkt Interrupt LB Testing.
INET - Intel Ethernet Controller Tests Table 3-6. INET Error Messages Error Message 3 Symptom or Cause EEPROM read error Acknowledgement for an EEPROM address is not being returned during a read access. EEPROM checksum error The checksum calculated from the EEPROM data does not match the checksum stored in the data itself. Unable to allocate PORT test memory Software is unable to allocate the memory needed for the PORT self test results.
Test Descriptions Table 3-6. INET Error Messages (Continued) Error Message 3 Symptom or Cause PCI Config Header Interrupt Line error. Written Value = 0xXX Read Value = 0xXX Value written to the PCI header Int Line register does not match the value read back. MDI control register error Value written to the MDI control register does not match the value read back. CU unexpectedly active Command Unit expected to be idle or suspended but is actually active.
EIDE - EIDE Tests EIDE - EIDE Tests This section describes the EIDE tests. These tests consist of REG, ACC, and RW. Entering EIDE without parameters causes all EIDE tests to execute in the order shown in the table below. Table 3-7. EIDE Test Group. Name Description REG Register Access Test. ACC Device Address Test. RW Read/Write Device (Destructive Device Access) To run an individual test, append the test name to the EIDE command.
Test Descriptions Prior to the execution of any of the EIDE tests, a validity check is performed on the CLUN/DLUN pair specified by the EIDE “cf” parameters. If either one of the values provided is invalid, the test aborts and an error message is displayed. 3 General Configuration Description: The EIDE diagnostics require some manual setup using the “cf” command prior to execution.
EIDE - EIDE Tests 3. Number of Sectors to Test. The “Number of Sectors to Test” field specifies the number of device sectors to be tested. For example, if two (2) sectors are specified and the test sector number field is specified as zero (0), then sectors 0 and 1 are tested. 4. Fill Data. The “Fill Data” field is used as a seed data value for tests that write to the disk.
Test Descriptions ACC - Device Access Command Input 3 PPCx-Diag>eide acc Description The ACC test performs five non-data EIDE commands: NOP, EXECUTE DEVICE DIAGNOSTICS, RESET, IDENTIFY DEVICE, and SEEK. The test is non-destructive since data is not read from or written to the disk itself. Data integrity of the disk is not altered. The BSY bit in the status register is first checked to verify that the device registers are valid (provided a device is attached).
EIDE - EIDE Tests 4. IDENTIFY DEVICE “IDENTIFY DEVICE” provides further testing of the EIDE interface in that it causes the first transfer of data across the channel, although in one direction only (data in). Several of the identify words provide configuration information to allow the test driver to properly construct a command packet. 5. SEEK. “SEEK” is issued three times. It first seeks block 0, then the last block, and then block 0 again.
Test Descriptions (ERROR MESSAGE) may be one of the following: Status Register Error. EIDE Device Access Test, Status Register Error: Register Address = _________, Error Bits = __, Bit Test Mask = __ Register Contents = __ 3 Walking Bit High Error. EIDE Device Access Test, Walking Bit High Error: Register Address = _________, Error Bits = __, Bit Test Mask = __ Walking Bit Low Error.
EIDE - EIDE Tests Seek Operation Error. EIDE Device Access Test, Seek Operation Error: (DEVICE ACCESS ERROR) 3 Start Unit Command Test Error. EIDE Device Access Test, Start Unit Command Test Error: (DEVICE ACCESS ERROR) Initialize Device Parameters Error.
Test Descriptions REG - Register Access Command Input 3 PPCx-Diag>eide reg Description The REG test performs non-intrusive device access for initial address and accessibility checks. Bit patterns of data written to and read from several of the ATA Task File registers are compared with expected values. Failures indicate addressing errors or data line corruption of data bits 0 through 7 only (D0-D7).
EIDE - EIDE Tests (ERROR MESSAGE) may be one of the following: Status Register Error. EIDE Register Test, Status Register Error: Register Address = _________, Error Bits = __, Bit Test Mask = __ Register Contents = __ Walking Bit High Error. EIDE Register Test, Walking Bit High Error: Register Address = _________, Error Bits = __, Bit Test Mask = __ Walking Bit Low Error.
Test Descriptions RW - Read/Write Device Command Input 3 PPC1-Diag>eide rw Note The test must first be enabled by setting the EIDE "cf" destructive test parameter to true. Description The RW test performs a write-read-verify cycle that verifies the overall integrity of the IDE/EIDE interface. The starting block and number of test sectors are defined by the EIDE "cf" parameters.
EIDE - EIDE Tests Response/Messages After the command has been issued, the following is displayed: 3 EIDE RW: EIDE Read/Write Tests... Running ---> If all parts of the test are completed correctly, then the test passes: EIDE RW: EIDE Read/Write Tests... Running ---> PASSED If any part of the test fails, the following is displayed: EIDE RW: EIDE Read/Write Tests... Running ---> FAILED EIDE/RW Test Failure Data: (ERROR MESSAGE) (ERROR MESSAGE) may be one of the following: Status Register Error.
Test Descriptions Block # = ____: (DEVICE ACCESS ERROR) Write Operation Error. 3 EIDE Read/Write Test, Write Operation Error: Block # = ____: (DEVICE ACCESS ERROR) Data Verification Error. EIDE Read/Write Test, Data Verification Error: Block # = ____: (DEVICE ACCESS ERROR) Write Operation (Restore Data) Error.
ISABRDGE - PCI/ISA Bridge Tests ISABRDGE - PCI/ISA Bridge Tests This section describes the individual Isabrdge (PCI/ISA Bridge) tests. Entering ISABRDGE without parameters causes all ISABRDGE tests to execute in the order shown in the following table. To run an individual test, add that test name to the ISABRDGE command. The individual tests are described in alphabetical order on the following pages. Table 3-8. ISABRDGE Test Group Name Description REG Register IRQ Interrupt http://www.motorola.
Test Descriptions IRQ - Interrupt Command Input 3 PPCx-Diag>ISABRDGE IRQ Description This test verifies that the ISABRDGE can generate interrupts. Response/Messages After the command has been issued, the following line is printed: ISABRDGE IRQ: Interrupt...................... Running ---> If all parts of the test are completed correctly, then the test passes. ISABRDGE IRQ: Interrupt......................
ISABRDGE - PCI/ISA Bridge Tests REG - Register Command Input: 3 PPC1-Diag>ISABRDGE REG Description This test verifies that the ISABRDGE registers can be written and read. Data patterns verify that every read/write bit can be modified. Response/Messages After the command has been issued, the following line is printed: ISABRDGE REG: Register....................... Running ---> If all parts of the test are completed correctly, then the test passes. ISABRDGE REG: Register.......................
Test Descriptions KBD8730x - Keyboard Controller Tests These sections describe the individual PC8730x Keyboard Controller, Mouse, and Keyboard Device tests. 3 Entering KBD8730x without parameters causes all KBD8730x tests to run in the order shown in the table below, except as noted. To run an individual test, add that test name to the KBD8730x command. The individual tests are described in alphabetical order on the following pages. Table 3-9.
KBD8730x - Keyboard Controller Tests KBCONF - Keyboard Device Confidence/Extended Command Input 3 PPCx-Diag>KBD8730x KBCONF Description This test performs an interface test of the keyboard controller to ensure correct operation of the interface to the keyboard device.
Test Descriptions KBFAT - Keyboard Test Command Input 3 PPCx-Diag>kbd8730x kbfat Description This test performs all the tests found in the keyboard device confidence/extended (kbconf) tests, issues an echo test to the keyboard device, issues a reset command to the keyboard device, and reads the keyboard device ID from the keyboard to ensure that the keyboard is plugged in and functioning correctly. These tests can only function with a keyboard device present.
KBD8730x - Keyboard Controller Tests KCCONF - Keyboard Controller Confidence/Extended Command Input 3 PPCx-Diag>KBD8730x KCCONF Description This test writes a command byte and reads it back from the PC8730x keyboard controller to place it in correct operation mode, and test that the registers can be accessed and that the data paths to the device are functioning. It then issues a keyboard controller self-command to invoke the internal diagnostics that are performed in the keyboard controller itself.
Test Descriptions KCEXT - Keyboard/Mouse Controller Extended Test Command Input 3 PPC1-Diag>KBD8730x KCEXT Description This test performs all the functions in the keyboard controller confidence tests (kcconf), tests the keyboard controller RAM locations by writing all possible byte values (0x00-0xff) to all possible RAM locations, and tests the Password functionality of the controller.
KBD8730x - Keyboard Controller Tests MSCONF - Mouse Device Confidence/Extended Command Input 3 PPCx-Diag>kbd8730x msconf Description This test performs an interface test of the keyboard controller to ensure correct operation of the interface to the mouse device. Response/Messages After the command has been issued, the following line is printed: KBD8730x MSCONF:Mouse Device Confidence/Extended:.
Test Descriptions MSFAT - Mouse Test Command Input 3 PPC1-Diag>KBD8730x MSFAT Description This test performs all the tests found in the mouse device confidence/extended (msconf) tests, reads the Mouse Device Type byte from the mouse device, and reads the status bytes from the mouse device to ensure that the mouse is plugged in and functioning correctly. These tests can only function with a mouse device present.
KBD8730x - Keyboard Controller Tests KBD8730x Error Messages The KBD8730x test group error messages generally take the following form: KBD8730x KBFAT: Keyboard Test:............... Running ---> FAILED KBD8730x/KBFAT Test Failure Data: Failure during command: XX Keyboard Controller timed out waiting for Output Buffer Full The first line of the test failure data identifies what type of failure occurred. The following line provides additional information about the failure. Table 3-10.
Test Descriptions Table 3-10. KBD8730x Error Messages (Continued) 3 Error Message Symptom or Cause Failure during command: XX Keyboard Controller timed out waiting for Output Buffer Full Failure of keyboard controller to send back a byte as a result of a command given to the keyboard controller itself. Indicates a possible problem with the keyboard controller embedded firmware or hardware.
KBD8730x - Keyboard Controller Tests Table 3-10. KBD8730x Error Messages (Continued) Error Message Symptom or Cause Password Test failed, password should exist, but doesn’t A password that was given to the keyboard controller was not stored properly, indicating a possible problem with the embedded firmware. Password Test failed, password should not exist, but does There was a failure in clearing out the password from the keyboard controller, indicating a possible problem with the embedded firmware.
Test Descriptions Table 3-10. KBD8730x Error Messages (Continued) 3 Error Message Symptom or Cause Keyboard Internal Diagnostic test failure: Check keyboard Invalid result code (%x) from Keyboard Internal Diagnostic test The keyboard device internal diagnostics test failed, indicating a problem with the keyboard device itself. Invalid ACK from Keyboard Read ID test.Getting XX Keyboard device failed to send an Acknowledge byte, indicating that it may be not present or working correctly.
L2CACHE - Level 2 Cache Tests L2CACHE - Level 2 Cache Tests This section describes the individual Level 2 (L2) Cache tests. Entering L2CACHE without parameters causes all L2CACHE tests to run in the order shown in the table below, except as noted. To run an individual test, add that test name to the L2CACHE command. The individual tests are described in alphabetical order on the following pages. Table 3-11.
Test Descriptions DISUPD - Disable Updating Command Input 3 PPC1-Diag>l2cache disupd Description This test performs a write/read test on the L2 Cache. The main objective of this test is to exercise the L2 Cache with Cache Updating disabled. The test flow is as follows: Turn on the cache with updating and WriteBack. Write an incrementing pattern to cache original region. Verify the incrementing pattern. Turn off cache updating. Write a decrementing pattern to displacing memory region. Turn off the cache.
L2CACHE - Level 2 Cache Tests ENUPD - Enable Updating Command Input 3 PPC1-Diag>l2cache enupd Description This test performs a write/read test on the L2 Cache. The main objective of this test is to exercise the L2 Cache with Cache Updating enabled. The test flow is as follows: Turn on the cache with WriteBack. Write an incrementing pattern to cache original region. Verify the incrementing pattern. Turn off cache. Write a decrementing pattern to original memory region.
Test Descriptions PATTERN - WriteThru Pattern Command Input 3 PPC1-Diag>l2cache pattern Description This test performs a write/read test on the L2 Cache. The main objective of this test is to exercise the L2 Cache WriteThru control, using multiple bit patterns. The test flow is as follows: Turn on the cache with WriteThru. Write an incrementing pattern to memory and the cache. Verify pattern is in the cache. Turn off the cache. Verify the pattern is outside of cache.
L2CACHE - Level 2 Cache Tests SIZE - Verify Cache Size Command Input 3 PPCx-Diag>l2cache size Description The main objective of this test is to verify the size of the L2 Cache, as indicated by the CPU Type Register. An error is reported if the size is incorrect. Response/Messages After the command has been issued, the following line is printed: SIZE: Verify Cache Size................ Running ---> If all parts of the test are completed correctly, then the test passes: SIZE: Verify Cache Size...........
Test Descriptions WBFL - Write Back w/Flush Command Input 3 PPCx-Diag>l2cache wbfl Description This test performs a write/read test on the L2 Cache. This test verifies that the device can be both accessed and that the L2 Cache Flush control works. The test flow is as follows: Turn off the cache. Write an incrementing pattern to memory and verify that the pattern is in memory. Turn on the cache with WriteBack. Write a decrementing pattern to the cache. Turn off the cache.
L2CACHE - Level 2 Cache Tests WBINV - Write Back w/Invalidate Command Input 3 PPCx-Diag>l2cache wbinv Description This test performs a write/read test on the L2 Cache. This test verifies that the device can be both accessed and that the L2 Cache Invalidate control is working. The test flow is as follows: Turn off the cache. Write an incrementing pattern to memory. Turn on the cache with WriteBack. Write a decrementing pattern to cache while invalidating the cache.
Test Descriptions WRTHRU - WriteThru Command Input 3 PPC1-Diag>l2cache wrthru Description This test performs a write/read test on the L2 Cache. This test verifies that the device can be both accessed and that the L2 Cache WriteThru control is working. The test flow is as follows: Turn on the cache with WriteThru. Write an incrementing pattern to memory and the cache. Verify the incrementing pattern. Turn off the cache. Verify that the incrementing pattern is in memory.
L2CACHE - Level 2 Cache Tests L2CACHE Error Messages The L2 Cache test group error messages generally take the following form: L2CACHE DISUPD: L2-Cache Disable Updating... Running ---> FAILED L2CACHE/DISUPD Test Failure Data: Data Miscompare Failure: Address =00040000, Expected =00000000, Actual =FFFFFFFF The first line of the failure identifies what type of failure occurred. The following line provides additional information about the failure. Table 3-12.
Test Descriptions NCR - 53C8xx SCSI I/O Processor Tests These sections describe the individual NCR 53C8xx (SCSI I/O Processor) tests. 3 The firmware now provides support for testing of multiple SCSI controllers within PCI configuration space. This means that the SCSI diagnostics can now be run on multiple SCSI controllers. This is “only” true for any firmware supported SCSI devices. Examples of where SCSI tests run include: 1. On a PowerPC board that has two (2) SCSI devices on the board. 2.
NCR - 53C8xx SCSI I/O Processor Tests The error message displays following the explanation of an NCR test pertain to the test being discussed. 3 http://www.motorola.
Test Descriptions ACC1 - Device Access Command Input 3 PPCx-Diag>NCR ACC1 Description This procedure tests the basic ability to access the NCR 53C8xx device. 1. All device registers are accessed (read) on 8-bit and 32-bit boundaries. (No attempt is made to verify the contents of the registers.) 2. The device data lines are checked by successive writes and reads to the SCRATCH register, by walking a 1 bit through a field of zeros and walking a 0 bit through a field of ones.
NCR - 53C8xx SCSI I/O Processor Tests Bus Error Information: Address ________ Data ________ Access Size __ Access Type _ Address Space Code _ Vector Number ___ 3 Unsolicited Exception: Program Counter ________ Vector Number ___ Status Register ____ Interrupt Level _ Notes 1. All error message data is displayed as hexadecimal values. 2. The Unsolicited Exception information is only displayed if the exception was not a Bus Error. 3. Access Size is displayed in bytes. 4.
Test Descriptions ACC2 - Register Access Command Input 3 PPCx-Diag>ncr acc2 Description This procedure tests the basic ability to access the NCR 53C8xx registers, by checking the state of the registers from a software reset condition and checking their read/write ability. Status registers are checked for initial clear condition after a software reset. Writable registers are written and read with a walking 1 through a field of zeros.
NCR - 53C8xx SCSI I/O Processor Tests SDID Register Error: Address =________, Expected =__, Actual =__ SODL Register Error: Address =________, Expected =__, Actual =__ 3 SXFER Register Error: Address =________, Expected =__, Actual =__ SCID Register Error: Address =________, Expected =__, Actual =__ DSA Register Error: Address =________, Expected =________, Actual =________ TEMP Register Error: Address =________, Expected =________, Actual =________ DMA Next Address Error: Address =________, Expected =__
Test Descriptions DFIFO - DMA FIFO Command Input 3 PPCx-Diag>NCR DFIFO Description This procedure tests the basic ability to write data into the DMA FIFO and retrieve it in the same order as written. The DMA FIFO is checked for an empty condition following a software reset, then the FBL2 bit is set and verified. The FIFO is then filled with 16 bytes of data in the four byte lanes verifying the byte lane full or empty with each write.
NCR - 53C8xx SCSI I/O Processor Tests DMA FIFO Parity Error: Address =________, Expected =__, Actual =__ DMA FIFO Byte Lane _ DMA FIFO Error: Address =________, Expected =__, Actual =__ DMA FIFO Byte Lane _ http://www.motorola.
Test Descriptions IRQ - Interrupts Command Input 3 PPCx-Diag>NCR IRQ Description This test verifies that interrupts can be generated and received and that the appropriate status is set. Response/Messages After the command has been issued, the following line is printed: NCR IRQ: NCR 53C8xx Interrupts.............. Running ---> If all parts of the test are completed correctly, then the test passes: NCR IRQ: NCR 53C8xx Interrupts..............
NCR - 53C8xx SCSI I/O Processor Tests Interrupt Status “SIP” bit will not clear Address =________, Expected =__, Actual =__ Interrupt Control Reg.
Test Descriptions Bus Error Information: Address ________ Data ________ Access Size __ Access Type _ Address Space Code _ Vector Number ___ 3 Unsolicited Exception: Program Counter ________ Vector Number ___ Status Register ____ Interrupt Level _ 3-74 Computer Group Literature Center Web Site
NCR - 53C8xx SCSI I/O Processor Tests PCI - PCI Access Command Input 3 PPC1-Diag>ncr pci Description This procedure tests the basic ability to access the PCI Configuration register address space for the NCR 53C8xx device. It performs a read of the address space and copies it into local memory and checks for bus errors and other catastrophic errors during this process. If no errors are detected, the NCR device is reset; otherwise the device is left in the test state.
Test Descriptions If it happens that the exception is a bus error, more information follows: Data-Access/Machine-Check Information: Address xxxxxxxx Data dddddddd Access Size nnnn Access Type xxxx Address Space Code xxxx bus error vector xxxxxxxx 3 Notes 1. All error message data is displayed as hexadecimal values. 2. Access Size is displayed in bytes. 3. Access Type is: 0 (write), or 1 (read).
NCR - 53C8xx SCSI I/O Processor Tests SCRIPTS - SCRIPTs Processor Command Input 3 PPCx-Diag>NCR SCRIPTS Description This test initializes the test structures and makes use of the diagnostic registers for test, as follows: ❏ Verifies that the following registers are initially clear: SIEN SCSI Interrupt Enable DIEN DMA Interrupt Enable SSTAT0 SCSI Status Zero DSTAT DMA Status ISTAT Interrupt Status SFBR SCSI First Byte Received ❏ Sets SCSI outputs in high impedance state, disables interrupts
Test Descriptions ❏ 3 Builds the “Memory Move instruction” SCRIPT in a script buffer to allow the “Source Address”, “Destination Address”, and “Byte Count” to be changed by use of the “config” command. If a parameter is changed, the only check for validity is the “Byte Count” during test structures initialization. The “Memory Move” SCRIPT copies the specified number of bytes from the source address to the destination address.
NCR - 53C8xx SCSI I/O Processor Tests Interrupt Status Reg. not initially clear Address =________, Expected =__, Actual =__ SCSI First Byte Received Reg. not initially clear Address =________, Expected =__, Actual =__ 3 SCSI First Byte Received Reg. not set Address =________, Expected =__, Actual =__ DMA Status “SSI” bit not set Address =________, Expected =__, Actual =__ Interrupt Status “DIP” bit not set Address =________, Expected =__, Actual =__ SCSI Status Zero Reg.
Test Descriptions SFIFO - SCSI FIFO Command Input 3 PPCx-Diag>ncr sfifo Description This procedure tests the basic ability to write data into the SCSI FIFO and retrieve it in the same order as written. The SCSI FIFO is checked for an empty condition following a software reset, then the SFWR bit is set and verified. The FIFO is then filled with 8 bytes of data verifying the byte count with each write. Next the SFWR bit is cleared and the FIFO read, verifying the byte count with each read.
PAR8730x - Parallel Port Test PAR8730x - Parallel Port Test This section describes the PC8730x parallel port test. This test is performed using only one processor. 3 You may enter PAR8730x with or without specifying the REG test. REG is the only test in the PAR8730x group. The REG test is described on the following page. Table 3-14. PAR8730x Test Group Name Description REG Register http://www.motorola.
Test Descriptions REG - Register Command Input: 3 PPCx-Diag>PAR8730x REG Description This test verifies that all of the PC8730x registers can be written and read. Data patterns verify that every read/write bit can be modified. Response/Messages After the command has been issued, the following line is printed: PAR8730x REG:PC8730x Parallel Port’s Register/Data..Running --> If all parts of the test are completed correctly, then the test passes: PAR8730x REG:PC8730x Parallel Port’s Register/Data..
UART - Serial Input/Output Tests UART - Serial Input/Output Tests These sections describe the individual UART tests. Entering UART without parameters causes all UART tests to run in the order shown in the table below, except as noted. To run an individual test, add that test name to the UART command. The individual tests are described in alphabetical order on the following pages. Table 3-15.
Test Descriptions BAUD - Baud Rates Command Input 3 PPCx-Diag>UART BAUD Description This test transmits 18 characters at various baud rates. The data is received and compared. If any protocol errors are created or the data is not correct when received, the test failed. The bauds tested are: 300 1200 2400 9600 19200 38400 Response/Messages After the command has been issued, the following line is printed: UART BAUD: Baud Rates..................
UART - Serial Input/Output Tests IRQ - Interrupt Request Command Input 3 PPCx-Diag>UART IRQ Description This test verifies that the UARTs can generate interrupts to the local processor. This is done using the transmitter empty interrupt from the UART under test. Response/Messages After the command has been issued, the following line is printed: UART IRQ: Interrupt Request............ Running ---> If all parts of the test are completed correctly, then the test passes: UART IRQ: Interrupt Request......
Test Descriptions LPBK - Internal Loopback Command Input 3 PPCx-Diag>UART lpbk Description This test transmits 18 characters at 9600 baud. The data is received and compared. If any protocol errors are created or the data is not correct when received, the test failed. Response/Messages After the command has been issued, the following line is printed: UART LPBK: Internal Loopback...........
UART - Serial Input/Output Tests LPBKE - External Loopback Command Input 3 PPCx-Diag>UART lpbke Description This test transmits 18 characters at 9600 baud. The data is received and compared. If any protocol errors are created or the data is not correct when received, the test failed. This test also verifies that modem control lines may be asserted and deasserted and that these signals are received back by the UART. This test does require an external loopback connector to be installed.
Test Descriptions REGA - Device/Register Access Command Input 3 PPCx-Diag>UART REGA Description This test performs a read test on all registers in the UARTs. It also verifies that the UART scratch registers are readable and writable. This test verifies that the device can be both accessed and that the data paths to the device are functioning. Response/Messages After the command has been issued, the following line is printed: UART REGA: Register Access.............
UART - Serial Input/Output Tests UART Error Messages The UART test group error messages generally take the following form: 3 UART BAUD: Baud Rates..............Running ---> FAILED UART/BAUD Test Failure Data: Data Miscompare Error: Address =XXXXXXXX, Register Index =XX Expected =XX, Actual =XX The first line of the test failure data identifies what type of failure occurred. The following line provides additional information about the failure. Table 3-16.
Test Descriptions Table 3-16. UART Error Messages (Continued) 3 Error Message Symptom or Cause Transmit/Receive character mismatch:channel XX Data transmitted does not match data received. Receiver Ready (Character Available) Time-Out PC16550 Base Address =XXXXXXXX, Channel =XX Baud Rate =XXXX The receiver has not received a character in the allotted time. DTR loopback to DSR and DCD Failed: Channel=XX When DTR was driven, DCD or DSR did not follow.
PCIBUS - Generic PCI/PMC Slot Tests PCIBUS - Generic PCI/PMC Slot Tests These sections describe the individual PCIBUS tests. These tests are available on all PowerPC boards. 3 Entering PCIBUS without parameters causes all PCIBUS tests to run in the order shown in the table below, except as noted. To run an individual test, add that test name to the PCIBUS command. The individual tests are described in alphabetical order on the following pages. Table 3-17.
Test Descriptions REG - PCI/PMC Slot Register Access Command Input 3 PPCx-Diag>pcibus reg Description The purpose of this function is to test any available PCI or PMC slots on PowerPC based boards. The test loops through all possible slots for the current board. The test then checks to see if the slot is inhabited, if not, the test is not performed. If a device is present, then access to the device’s PCI configuration space is made, and the interrupt line register is written with a sixteen byte pattern.
PCIBUS - Generic PCI/PMC Slot Tests PCIBUS Error Messages The PCIBUS test group error messages generally take the following form: 3 PCIBUS REG: PCI/PMC:........... Running ---> FAILED BIST failed to complete. The first line of the test failure data identifies what type of failure occurred. Table 3-18. PCIBUS Error Messages Error Message Symptom or Cause BIST failed to complete. The Built-In-Self-Test of the PCI or PMC device did not complete before timing out. Interrupt Line Register Write Error.
Test Descriptions RAM - Local RAM Tests These sections describe the individual Random Access Memory (RAM) tests. 3 Entering RAM without parameters causes all RAM tests to execute in the order shown in the table below. To run an individual test, add that test name to the RAM command. The individual tests are described in alphabetical order on the following pages. Table 3-19.
RAM - Local RAM Tests ADR - Memory Addressing Command Input 3 PPCx-Diag>RAM ADR Description This is the memory addressability test, the purpose of which is to verify addressing of memory in the range specified by the configuration parameters for the RAM test group. Addressing errors are sought by using a memory locations address as the data for that location. This test is coded to use only 32-bit data entities. The test proceeds as follows: 1. A Locations Address is written to its location (n). 2.
Test Descriptions RAM ADR: Addressability............
RAM - Local RAM Tests ALTS - Alternating Ones/Zeros Command Input 3 PPCx-Diag>RAM ALTS Description This test verifies addressing of memory in the range specified by the configuration parameters for the RAM test group. Addressing errors are sought by using a memory locations address as the data for that location. This test is coded to use only 32-bit data entities. The test proceeds as follows: 1. Location (n) is written with data of all bits 0. 2. The next location (n+4) is written with all bits 1. 3.
Test Descriptions BTOG - Bit Toggle Command Input 3 PPCx-Diag>ram btog Description The memory range is specified by the RAM test directory configuration parameters. (Refer to CF - Test Group Configuration Parameters Editor in Chapter 2.) The RAM test directory configuration parameters also determine the value of the global random data seed used by this test. The global random data seed is incremented after it is used by this test. This test uses the following test data pattern generation algorithm: 1.
RAM - Local RAM Tests Response/Messages After the command has been issued, the following line is printed: RAM BTOG: Bit Toggle........................ Running ---> 3 If all parts of the test are completed correctly, then the test passes: RAM BTOG: Bit Toggle........................ Running ---> PASSED If the test fails, then the display appears as follows: RAM BTOG: Bit Toggle........................
Test Descriptions CODE - Code Execution/Copy Command Input 3 PPCx-Diag>RAM CODE Description Copy test code to memory and execute. The code in the memory under test copies itself to the next higher memory address and executes the new copy. This process is repeated until there is not enough memory, as specified by the configuration parameters, to perform another code copy and execution. Response/Messages After the command has been issued, the following line is printed: RAM CODE: Code Execution/Copy.......
RAM - Local RAM Tests MARCH - March Pattern Command Input 3 PPCx-Diag>ram march Description This is the memory march test, the purpose of which is to verify addressing of memory in the range specified by the configuration parameters for the RAM test group. Addressing errors are sought by writing a pattern and its complement to each location. This test is coded to use only 32-bit data entities. The test proceeds as follows: 1.
Test Descriptions PATS - Data Patterns Command Input 3 PPCx-Diag>RAM PATS Description If the test address range (test range) is less than 8 bytes, the test immediately returns pass status. The effective test range end address is reduced to the next lower 8-byte boundary if necessary. Memory in the test range is filled with all ones ($FFFFFFFF).
RAM - Local RAM Tests PED - Local Parity Memory Error Detection Command Input 3 PPCx-Diag>RAM PED Description The memory range and address increment is specified by the RAM test directory configuration parameters. (Refer to CF - Test Group Configuration Parameters Editor in Chapter 2.) First, each memory location to be tested has the data portion verified by writing/verifying all zeros, and all ones.
Test Descriptions Here (error message) is one of the following: If a data verification error occurs: Data Miscompare Error: Address =________, Expected =________, Actual =________ 3 If an unexpected exception, such as a parity error being detected as the parity bit was being toggled: Unexpected Exception Error, Vector =________ Address Under Test =________ If no exception occurred when data with bad parity was read: Parity Error Detection Exception Did Not Occur Exception Vector =________ Address Under
RAM - Local RAM Tests PERM - Permutations Command Input 3 PPCx-Diag>RAM PERM Description This command performs a test which verifies that the memory in the test range can accommodate 8-bit, 16-bit, and 32-bit writes and reads in any combination. The test range is the memory range specified by the RAM test group configuration parameters for starting and ending address. If the test address range (test range) is less than 16 bytes, the test immediately returns pass status.
Test Descriptions QUIK - Quick Write/Read Command Input 3 PPCx-Diag>ram quik Description Each pass of this test fills the test range with a data pattern by writing the current data pattern to each memory location from a local variable and reading it back into that same register. The local variable is verified to be unchanged only after the write pass through the test range. This test uses a first pass data pattern of 0, and $FFFFFFFF for the second pass.
RAM - Local RAM Tests REF - Memory Refresh Testing Command Input 3 PPCx-Diag>RAM REF Description The memory range and address increment is specified by the RAM test directory configuration parameters. (Refer to CF - Test Group Configuration Parameters Editor in Chapter 2.) First, the real time clock is checked to see if it is functioning properly. Second, each memory location to be tested has the data portion verified by writing/verifying all zeros, and all ones.
Test Descriptions RTC is in write mode, invoke SET command. Or: RTC is in read mode, invoke SET command.
RAM - Local RAM Tests RNDM - Random Data Command Input 3 PPCx-Diag>RAM RNDM Description The test block is the memory range specified by the RAM test group configuration parameters. The test proceeds as follows: 1. A random pattern is written throughout the test block. 2. The random pattern complemented is written throughout the test block. 3. The complemented pattern is verified. 4. The random pattern is rewritten throughout the test block. 5. The random pattern is verified.
Test Descriptions RTC - MK48Txx Timekeeping Tests These tests check the BBRAM and clock portions of the MK48Txx Real Time Clock (RTC) chips. 3 Entering RTC without parameters causes all RTC tests to execute in the order shown in the table below, except as noted. To run an individual test, add that test name to the RTC command. The individual tests are described in alphabetical order on the following pages. Table 3-20.
RTC - MK48Txx Timekeeping Tests ADR - MK48Txx BBRAM Addressing Command Input 3 PPCx-Diag>RTC ADR Description This test is designed to assure proper addressability of the MK48Txx BBRAM. The algorithm used is to fill the BBRAM with data pattern “a”, a single address line of the MK48Txx is set to one, and pattern “b” is written to the resultant address. All other locations in the BBRAM are checked to ensure that they were not affected by this write.
Test Descriptions If debugger system memory cannot be allocated for use as a save area for the BBRAM contents: RAM allocate 3 memc.next=________ memc.
RTC - MK48Txx Timekeeping Tests ALARM - Alarm Interrupt Command Input 3 PPCx-Diag>rtc alarm Description This test sets the alarm of the Real Time Clock (RTC) MK48Txx to go off every second, and verifies that interrupt IRQ8 occurs and the AF (Alarm Flag) bit of the RTC is set. Response/Messages After the command has been issued, the following line is printed: RTC ALARM: MK48Txx Alarm Interrupt........
Test Descriptions CLK - Real Time Clock Function Command Input 3 PPCx-Diag>RTC CLK Description This test verifies the functionality of the Real Time Clock (RTC). This test does not check clock accuracy. This test requires approximately nine seconds to run. At the conclusion of the test, nine seconds are added to the clock time to compensate for the test delay. Because the clock can only be set to the nearest second, this test may induce one second of error into the clock time.
RTC - MK48Txx Timekeeping Tests If the predetermined number of reads are made before the seconds register changed, the following message is printed: RTC not running The RTC time registers are configured for reading. A pre-determined number of MPU “do nothing” loops are executed.
Test Descriptions RAM - Battery Backed-Up RAM Command Input 3 PPCx-Diag>rtc ram Description This test performs a data test on each BBRAM location of the MK48Txx “Timekeeper” RAM. RAM contents are unchanged upon completion of test, regardless of pass or fail test return status. This test is coded to test only byte data entities. The test proceeds as follows: For each of the following patterns: $1, $3, $7, $f, $1f, $3f, $7f; for each valid byte of the “Timekeeper” RAM: 1.
RTC - MK48Txx Timekeeping Tests WATCHDOG - Watchdog Time-Out Reset Command Input 3 PPCx-Diag>rtc watchdog Description This test sets the Real Time Clock’s Watchdog Timer to time out in one second. If the Watchdog Timer is functional, the WDF (Watchdog Flag) bit will be set and a microprocessor reset will be generated. ! If this test passes, the Real Time Clock will reset the board.
Test Descriptions SCC - Serial Communication Controller (Z85230) Tests 3 These sections describe the individual Serial Communication Controller (SCC) tests. These tests are not available on the MVME230x boards. Entering SCC without parameters causes all SCC tests to run in the order shown in the table below, except as noted. To run an individual test, add that test name to the SCC command. The individual tests are described in alphabetical order on the following pages. Table 3-21.
SCC - Serial Communication Controller (Z85230) Tests Example: PPC1-Diag>CF SCC SCC Memory Space Base Address =80000840?RETURN Internal-Loopback/Baud-Rates Port Mask =00000003? 2 3 (Bit 0 selects port 0, Bit 1 selects port 1; see note below.) External-Loopback/Modem-Control Port Mask=00000003? The first parameter is the base address space for the Z85230 devices. This is preset for the PowerPC family of boards and should not be changed. The next two parameters are the port selection masks.
Test Descriptions ACCESS - Device/Register Access Command Input 3 PPCx-Diag>SCC ACCESS Description This test performs a write/read test on two registers in the Z85230. This test verifies that the device can be both accessed and that the data paths to the device are functioning. Response/Messages After the command has been issued, the following line is printed: SCC ACCESS: Device/Register Access......
SCC - Serial Communication Controller (Z85230) Tests BAUDS - Baud Rates Command Input 3 PPCx-Diag>scc bauds Description This test transmits 256 characters at various baud rates. The data is received and compared. If any protocol errors are created or the data is not correct when received, the test failed.
Test Descriptions DMA - Receive/Transmit DMA Command Input 3 PPCx-Diag>SCC DMA Description This test will verify that the SCC can transmit and receive via internal loopback, a 256-byte block of data that consists of all numbers between 0x00 and 0xFF. The test will be performed under DMA control. A match of the contents of the transmit and receive buffers will be verified. Due to the nature of DMA, use of the ISA Bridge IC is also necessary.
SCC - Serial Communication Controller (Z85230) Tests In the first case, the Serial Port 3 Receiver (Z85230 Port A Rx, ISA DMA Controller 1 and Channel 0) has reached terminal count before receiving all the data. In the second case, the Serial Port 4 Receiver (Z85230 Port B Rx, ISA DMA Controller 2 and Channel 5) has reached terminal count before receiving all the data. If the receiver buffer is filled with data before terminal count, it may still be an incorrect match to the data transmitted.
Test Descriptions ELPBCK - External Loopback Command Input 3 PPCx-Diag>SCC ELPBCK Description This test transmits 256 characters at 38400 baud. The data is received and compared. If any protocol errors are created or the data is not correct when received, the test fails. This test does require an external loopback connector to be installed.
SCC - Serial Communication Controller (Z85230) Tests ILPBCK - Internal Loopback Command Input 3 PPCx-Diag>SCC ILPBCK Description This test transmits 256 characters at 38400 baud. The data is received and compared. If any protocol errors are created or the data is not correct when received, the test failed. Note Because of the design of the Z85230, when internal loopback testing is performed, data is still transmitted out of the device on the TxD line.
Test Descriptions IRQ - Interrupt Request Command Input 3 PPCx-Diag>scc irq Description This test verifies that the Z85230 can generate interrupts to the local processor. This is done using the baud rate zero counter interrupt from the Z85230. Response/Messages After the command has been issued, the following line is printed: SCC IRQ: Interrupt Request.............. Running ---> If all parts of the test are completed correctly, then the test passes: SCC IRQ: Interrupt Request.........
SCC - Serial Communication Controller (Z85230) Tests MDMC - Modem Control Command Input 3 PPCx-Diag>SCC MDMC Description This test verifies that the Z85230 can negate/assert selected modem control lines and that the appropriate input control functions properly. This test does require an external loopback connector to be installed.
Test Descriptions SCC Error Messages The SCC test group error messages generally take the following form: 3 SCC BAUDS: Baud Rates....................... Running ---> FAILED SCC/BAUDS Test Failure Data: Transmit/Receive Character Miscompare Error: Expected =55, Actual =5F SCC Base Address =80000840, Channel =01 Baud Rate =1200 The first line of the failure identifies what type of failure occurred. The following line provides additional information about the failure. Table 3-22.
SCC - Serial Communication Controller (Z85230) Tests Table 3-22. SCC Error Messages (Continued) Error Message Symptom or Cause SCC Receiver Error: Status =xx Break Sequence detected in the RXD stream SCC Base Address =xxxxxxxx, Channel =xx Baud Rate =xxxx An unexpected break was received during testing. Transmit/Receive Character Miscompare Error: Expected =xx, Actual =xx SCC Base Address =xxxxxxxx, Channel =xx Baud Rate =xxxx Data transmitted does not match data received.
Test Descriptions VGA54XX - Video Diagnostics Tests These sections describe the individual Video Graphics Array (VGA) tests. These tests are not available on PowerPC boards that don’t have a VGA device on-board. 3 The firmware now provides support for testing of multiple VGA controllers within PCI configuration space. This means that the VGA diagnostics can now be run on multiple Cirrus Logic VGA 54XX Controllers. This is “only” true for any firmware supported VGA devices.
VGA54XX - Video Diagnostics Tests Table 3-23. VGA543X Test Group (Continued) Name Description PAL Color Palette PCI PCI Header Verification PELM Pixel Mask Register SEQR Sequencer Registers VRAM Video Memory BLT Bit Blitter http://www.motorola.
Test Descriptions ATTR - Attribute Register Command Input 3 PPCx-Diag>VGA54XX ATTR Description This test verifies the correct operation of the VGA Attribute Registers. The test proceeds as follows: 1. Each Attribute Register is initialized with one of 256 possible values, with reserved bits being masked off to a value of zero. 2. The Attribute Register is read back to verify that the data that was written to the register in step 1 was written correctly.
VGA54XX - Video Diagnostics Tests BLT - Bit Blitter Command Input 3 PPCx-Diag>vga543x blt Description This test verifies that the Bit BLT of the Cirrus Logic CL-54XX chip is functioning correctly by invoking a blitter operation to copy a block of data from system memory to video DRAM, then invoking a blitter operation to copy the block from one area in video DRAM to another and then finally a blitter operation to copy the block of data back into system memory.
Test Descriptions CRTC - CRT Controller Registers Command Input 3 PPCx-Diag>VGA54XX CRTC Description This test verifies the correct operation of the VGA CRT Controller Registers. The test proceeds as follows: 1. Each CRT Controller Register is initialized with one of 256 possible values, with reserved bits being masked off to a value of zero. 2. The CRT Controller Register is read back to verify that the data that was written to the register in step 1 was written correctly.
VGA54XX - Video Diagnostics Tests DSTATE - DAC State Register Command Input 3 PPCx-Diag>vga54xx dstate Description Test the DAC State Register. This test verifies that the VGA controller changes when set to the various mode states. Response/Messages After the command has been issued, the following line is printed: VGA54XX DSTATE: DAC State Registers......Running -> If all parts of the test are completed correctly, then the test passes: VGA54XX DSTATE: DAC State Registers..
Test Descriptions EXTN - Extended Registers Command Input 3 PPCx-Diag>VGA54XX EXTN Description This test verifies that the Extended Sequencer, Graphics, CRT Controller, and Pel Mask Registers are correctly functioning. Each possible pattern for each of the registers is used with reserved bits being masked to a value of zero. 1. Each extended register is initialized with one of 256 possible values, with reserved bits being masked off to a value of zero. 2.
VGA54XX - Video Diagnostics Tests GRPH - Graphics Controller Registers Command Input 3 PPCx-Diag>VGA54XX GRPH Description This test verifies the correct operation of the VGA Graphics Controller Registers. The test proceeds as follows: 1. Each Graphics Controller Register is initialized with one of 256 possible values, with reserved bits being masked off to a value of zero. 2.
Test Descriptions MISC - Miscellaneous Register Command Input 3 PPCx-Diag>VGA54XX MISC Description This test verifies the correct operation of the VGA Miscellaneous Control Register. The test proceeds as follows: 1. Each Graphics Controller Register is initialized with one of 256 possible values, with reserved bits being masked off to a value of zero. 2. The Graphics Controller Register is read back to verify that the data that was written to the register in step 1 was written correctly.
VGA54XX - Video Diagnostics Tests PAL - Color Palette Command Input 3 PPCx-Diag>VGA54XX PAL Description This test verifies the correct operation of the 256 possible color palette entries. Each palette red, green, and blue entry is verified by checking for the setting of all bits to 1s and 0s. Response/Messages After the command has been issued, the following line is printed: VGA54XX PAL: Palette Register.........
Test Descriptions PCI - PCI Header Verification Command Input 3 PPCx-Diag>vga54XX pci Description This is the PCI header verification test, the purpose of which is to verify that the system has a supported Cirrus Logic graphics controller. The test proceeds as follows: ❏ Searches the PCI bus for the Cirrus Logic controller by looking at the chip identification register. If a supported Cirrus Logic controller is found, the test passes.
VGA54XX - Video Diagnostics Tests PELM - Pixel Mask Register Command Input 3 PPCx-Diag>VGA543X PELM Description This test verifies the correct operation of the VGA Pixel Mask Register. The test proceeds as follows: 1. The Pixel Mask Register is initialized with one of 256 possible values, with reserved bits being masked off to a value of zero. 2. The Pixel Mask Register is read back to verify that the data that was written to the register in step 1 was written correctly.
Test Descriptions SEQR - Sequencer Registers Command Input 3 PPCx-Diag>VGA54XX SEQR Description This test verifies the correct operation of the VGA Sequencer Controller Registers. The test proceeds as follows: 1. Each Sequencer Controller Register is initialized with one of 256 possible values, with reserved bits being masked off to a value of zero. 2. The Sequencer Controller Register is read back to verify that the data that was written to the register in step 1 was written correctly.
VGA54XX - Video Diagnostics Tests VRAM - Video Memory Command Input 3 PPCx-Diag>VGA54XX VRAM Description This test verifies the first 1 megabyte of video RAM. Each location is written as a 16-bit value with alternating 1s and 0s. Response/Messages After the command has been issued, the following line is printed: VGA54XX VRAM: Cirrus vga54Xx VRAM Test...Running ---> If all parts of the test are completed correctly, then the test passes: VGA54XX VRAM: Cirrus vga54Xx VRAM.Test...
Test Descriptions VME2 - VME Interface ASIC Tests This section lists the individual VMEchip2 tests, but does not describe them. These tests are available only on the MVME160x PowerPC boards. For all other PowerPC boards, these tests are bypassed. 3 Entering VME2 without parameters causes all VME2 tests to execute in the order shown in the table below. To run an individual test, add that test name to the VME2 command. Table 3-24.
VME3- Universe VME to PCI Bridge Tests Entering VME3 without parameters causes all VME3 tests to run in the order shown in the table below, except as noted. To run an individual test, add that test name to the VME3 command. The individual tests are described in alphabetical order on the following pages. Table 3-25.
Test Descriptions REGR - Register Read Command Input 3 PPCx-Diag>VME3 REGR Description This test reads all registers in the Universe chip. The 4 Kilobyte UCSR space is read as 32-bit, 16-bit, and 8-bit values. No check will be made as to the actual contents of the registers. An error in this test would be reported as an unsolicited exception. Response/Messages After the command has been issued, the following line is printed: VME3 regr:..................................
VME3- Universe VME to PCI Bridge Tests REGW - Register Write/Read Command Input 3 PPCx-Diag>VME3 regw Description This test performs a “read / modify / read / restore / verify” sequence to selected registers in the Universe chip. The registers are part of the 4 Kilobyte UCSR, and are accessed as PCI Memory space. The values written are chosen in order to verify as many device address and data lines as is safely possible.
Test Descriptions VME3 Error Messages The VME3 test group error messages generally take the following form: 3 VME3 regr: Register Read:.............Running ---> FAILED VME3 regr Test Failure Data: Detail of Failure Table 3-26. VME3 Error Messages Error Message Notes Universe Vendor ID seen in config space, but VME Present bit indicates chip isn’t installed.
Z8536 - Counter/Timer Tests Z8536 - Counter/Timer Tests This section describes the individual Z8536 CIO counter/timer tests. These tests are not available on the MVME230x PowerPC boards. Entering Z8536 without parameters causes all Z8536 tests to execute in the order shown in the following table. To run an individual test, add that test name to the Z8536 command. The individual tests are described in alphabetical order on the following pages. Table 3-27.
Test Descriptions CNT - Counter Command Input 3 PPCx-Diag>z8536 cnt Description This test verifies the functionality of the counter in the Z8536 chip. Response/Messages After the command has been issued, the following line is printed: Z8536 CNT: Counter.......................... Running ---> If all parts of the test are completed correctly, then the test passes: Z8536 CNT: Counter..........................
Z8536 - Counter/Timer Tests IRQ - Interrupt Command Input 3 PPCx-Diag>Z8536 IRQ Description This test verifies that the Z8536 can generate interrupts. Response/Messages After the command has been issued, the following line is printed: Z8536 IRQ: Interrupt.......................Running ---> If all parts of the test are completed correctly, then the test passes: Z8536 IRQ: Interrupt.................
Test Descriptions LNK - Linked Counter Command Input 3 PPCx-Diag>Z8536 LNK Description This test verifies the functionality of the timers in the Z8536. Counter 1 output is linked to counter 2 input. This test does not check timer accuracy. Response/Messages After the command has been issued, the following line is printed: Z8536 LNK: Linked Counter................... Running ---> If all parts of the test are completed correctly, then the test passes: Z8536 LNK: Linked Counter.............
Z8536 - Counter/Timer Tests REG - Register Command Input 3 PPCx-Diag>z8536 reg Description This test verifies that all of the Z8536 registers can be written and read. Data patterns verify that every read/write bit can be modified. Response/Messages After the command has been issued, the following line is printed: Z8536 REG: Register.........................Running ---> If all parts of the test are completed correctly, then the test passes: Z8536 REG: Register...................
Test Descriptions 3 3-154 Computer Group Literature Center Web Site
ARelated Documentation A Motorola Computer Group Documents The Motorola publications listed below are referenced in this manual. You can obtain paper or electronic copies of Motorola Computer Group publications by: ❏ Contacting your local Motorola sales office ❏ Visiting Motorola Computer Group’s World Wide Web literature site, http://www.motorola.com/computer/literature . Table A-1.
A Motorola Computer Group Documents Table A-1.
Related Documentation Microprocessor and Controller Documents For additional information, refer to the following table for manufacturers’ data sheets or user’s manuals. As an additional help, a source for the listed document is also provided. Please note that in many cases, the information is preliminary and the revision levels of the documents are subject to change without notice.. Table A-2.
A Microprocessor and Controller Documents Table A-2. Microprocessor and Controller Documents (Continued) Publication Number Document Title and Source PowerPC 604TM RISC Microprocessor User’s Manual Literature Distribution Center for Motorola Telephone: (800) 441-2447 FAX: (602) 994-6430 or (303) 675-2150 E-mail: ldcformotorola@hibbertco.
Related Documentation Table A-2. Microprocessor and Controller Documents (Continued) Document Title and Source Publication Number AlpineTM VGA Family - CL-GD543X/’4X Technical Reference Manual Fourth Edition Cirrus Logic, Inc.
A Microprocessor and Controller Documents Table A-2. Microprocessor and Controller Documents (Continued) Publication Number Document Title and Source PC87307VUL ( Super I/OTM Enhanced Sidewinder Lite) Floppy Disk Controller,, Keyboard Controller, Real-Time Clock, Dual UARTs, IEEE 1284 Parallel Port, and IDE Interface National Semiconductor Corporation Customer Support Center (or nearest Sales Office) 2900 Semiconductor Drive P.O.
Related Documentation Table A-2. Microprocessor and Controller Documents (Continued) Document Title and Source Publication Number SYM 53CXX (was NCR 53C8XX) Family PCI-SCSI I/O Processors Programming Guide Symbios Logic Inc. 1731 Technology Drive, suite 600 San Jose, CA95110 Telephone: (408) 441-1080 Hotline: 1-800-334-5454 T72961II SCC (Serial Communications Controller) User’s Manual (for Z85230 and other Zilog parts) Zilog, Inc. 210 East Hacienda Ave.
A Microprocessor and Controller Documents Table A-2. Microprocessor and Controller Documents (Continued) Publication Number Document Title and Source Z8536 CIO Counter/Timer and Parallel I/O Unit Product Specification and User’s Manual (in Z8000® Family of Products Data Book) Zilog, Inc. 210 East Hacienda Ave.
Related Documentation Related Specifications For additional information, refer to the following table for related specifications. As an additional help, a source for the listed document is also provided. Please note that in many cases, the information is preliminary and the revision levels of the documents are subject to change without notice. Table A-3.
A Related Specifications Table A-3. Related Specifications (Continued) Publication Number Document Title and Source VME64 Specification VITA (VMEbus International Trade Association) 7825 E. Gelding Drive, Suite 104 Scottsdale, Arizona 85260-3415 Telephone: (602) 951-8866 FAX: (602) 951-0720 ANSI/VITA 1-1994 NOTE: An earlier version of this specification is available as: Versatile Backplane Bus: VMEbus Institute of Electrical and Electronics Engineers, Inc.
Related Documentation Table A-3. Related Specifications (Continued) Document Title and Source Publication Number Bidirectional Parallel Port Interface Specification Institute of Electrical and Electronics Engineers, Inc. Publication and Sales Department 345 East 47th Street New York, New York 10017-21633 Telephone: 1-800-678-4333 IEEE Standard 1284 Peripheral Component Interconnect (PCI) Local Bus Specification, Revision 2.1 PCI Special Interest Group 2575 NE Kathryn St.
A Related Specifications Table A-3.
Index Numerics 53C8xx SCSI I/O Processor Tests - NCR 3-64 A ACC1 3-66 ACC2 3-68 ACCESS 3-120 Address and Data Parity Error status 3-9 addressing memory 3-95 ADR 3-95, 3-111 ADR (BBRAM Addressing) MK48Txx Timekeeping Tests 3-111 AEM 2-2 ALARM 3-113 ALARM interrupt - ALARM 3-113 Alternating Ones/Zeros - ALTS 3-97 ALTS 3-97 Append Error Messages Mode - AEM 2-2 ATA device use with EIDE tests 3-29 ATTR 3-132 Attribute Register - ATTR 3-132 Audio Codec Tests - CS4231 3-29 AUI connection 3-8 B Battery Backed-Up
Index configuration parameters 2-3 Connector CNCTR 3-8 Continuous Load CLOAD 3-7 controller device documents A-3 controller, Cirrus Logic 3-140 conventions used in the manual 4 Counter - CNT 3-150 Counter/Timer Tests CNT (Counter) 3-150 IRQ (Interrupt) 3-151 LNK (Linked Counter) 3-152 REG (Register) 3-153 Counter/Timer Tests - Z8536 3-149 CRT Controller Registers - CRTC 3-134 CRTC 3-134 CS4231 - Audio Codec Tests 3-29 D I N D E X DAC State Register - DSTATE 3-135 DE 2-4 debugger directory 1-2 prompt 1-2
clear 2-3 DEC21x40 3-15 display 2-4 KBD8730x 3-51, 3-148 L2CACHE 3-63 PCIBUS 3-93 SCC 3-63, 3-128 UART 3-89 Ethernet Controller Tests - DEC21x40 3-4 examples of command entry 1-3 Extended PCI Register Access - XREGA 3-14 Extended Registers - EXTN 3-136 External Loopback - ELPBCK 3-124 External Loopback - LPBKE 3-87 EXTN 3-136 G general commands 2-1 Generic PCI/PMC Slot Tests - PCIBUS 3-91 Graphics Controller Register 3-138 Graphics Controller Registers - GRPH 3-137 graphics tests 3-130 GRPH 3-137 H HE 1-2
Index KCCONF (Keyboard Controller Confidence/Extended 3-47 KCEXT (Keyboard/Mouse Controller Extended Test) 3-48 MSCONF (Mouse Device Confidence/Extended) 3-49 MSFAT (Mouse Test) 3-50 Keyboard Device Confidence/Extended KBCONF 3-45 Keyboard Test - KBFAT 3-46 Keyboard/Mouse Controller Extended Test KCEXT 3-48 L I N D E X L2CACHE Error Messages 3-63 LA 2-8 LC 2-9 LE 2-9 Level 2 Cache Tests DISUPD (Disable Updating) 3-56 ENUPD (Enable Updating) 3-57 PATTERN (Write Thru Pattern) 3-58 SIZE (Verify Cache Size)
O Q overview of firmware 1-1 QST 2-13 Quick Self Test - QST 2-13 Quick Write/Read - QUIK 3-106 QUIK 3-106 P PAL 3-139 PAR8730x - Parallel Port Test 3-81 parallel interface tests 3-2 Parallel Interface Tests - CSL1283 3-2 Parallel Port Test REG (Register) 3-82 Parallel Port Test - PAR8730x 3-81 pass count 2-5 PATS 3-102 PATTERN 3-58 pattern march 3-101 PC8730x - Keyboard Controller Tests 3-44 PCI 3-75, 3-140 PCI Access - PCI 3-75 PCI Bus Tests REG (PCI/PMC Slot Register Access) 3-92 PCI Header Register A
Index I N D E X SCSI I/O Processor Tests PCI (PCI Access) 3-75 SCRIPTS (SCRIPTs Processor) 3-77 SCSI I/O Processor Tests - NCR 3-64 SCSI Tests ACC1 - Device Access 3-66 SD 2-12 SE 2-13 Self Test - ST 2-13 Self Test Mask 2-11 SEQR 3-142 Sequencer Controller Register 3-142 Sequencer Registers - SEQR 3-142 Serial I/O Tests BAUD (Baud Rates) 3-84 IRQ (Interrupt Request) 3-85 LPBK (Internal Loopback) 3-86 REGA (Device/Register Access 3-88 SERREN 3-9 SERT System Enable Response Test 3-21 SFIFO 3-80 Single Packe
WriteThru - WRTHRU 3-62 WriteThru Pattern - PATTERN 3-58 WRTHRU 3-62 X XREGA 3-14 Z ZE 2-15 Zero Pass Count - ZP 2-15 ZP 2-15 I N D E X http://www.motorola.
Index I N D E X IN-8 Computer Group Literature Center Web Site
