Specifications

D
evice Driver Programming
7-6
Byte-Ordering and Alignment 7
The byte-ordering convention used in the Power Hawk 620/640 platform is Big Endian.In
this model, the most significant byte (MSB) always has the lowest address. This provides a
consistency of addressing which is independent of the word size of the machine. See
Figure 7-3, “Big Endian Bit and Byte Notation” for more information. (Note that the
depicted bit ordering (with bit 31 most significant) is applicable to I/O addressing. The bit
ordering of the PowerPC 604 is the opposite (with bit 0 most significant). Byte ordering
for both I/O and the PowerPC 604 is the same.)
Byte ordering on the PCI bus is little endian. The various bridge chips provide appropriate
translation from one ordering to the other for VME bus drivers. However, drivers written
for PCI devices must be aware of the difference and modify device addresses accordingly.
During I/O transfers, the system expects the addresses of all words even addresses— that
is, zero, two, four, six, eight, and so on. Similarly, the system expects that all longword
addresses are divisible by four—that is zero, four, eight, twelve, and so on. Finally, the
system expects all double-longword addresses to be divisible by eight—that is, zero, eight,
sixteen, etc.
NOTE
Attempting an I/O transfer using non-aligned data types in a
driver program causes a fatal exception error on Power Hawk
620/640 platforms. In other words, alignment errors are not
recoverable in hardware.
Figure 7-3. Big Endian Bit and Byte Notation
LOW
ADDRESS
HIGHER
ADDRESS
LOW ADDRESS = MSB
MSB
LSB
7
0
15
16
23
24
31
0
0
7
8
7
8
15
MSB
LSB