Specifications

PowerMAXION Hardware Environmen
t
6-9
Bus Arbitration 6
Because a bus provides the capability to support multiple bus masters, a means of resolv-
ing the contention of concurrent requests for bus mastership by multiple devices must be
provided. This is the purpose of a special unit on the VME bus, the VME bus arbiter.
Bus arbitration is important only for devices that can act as bus masters. This is indicated
in a device specification as either “bus master” or “DMA Operation.” Because bus arbitra-
tion is implementation-dependent, the following explains what you need to know about
arbitration on the PowerMAXION platform.
Bus Request Levels 6
The VMEbus specification defines extensive bus arbitration options. The options are
implemented using four bus request levels and a bus busy (BBSY) signal.
A device on the VME bus becomes the bus master by asserting bus request and receiving
bus grant. The new bus master then asserts the bus busy (BBSY) signal until it is ready to
relinquish the bus. During this time, the device is the only one allowed to generate bus
addresses until it releases the bus.
NOTE
The VMEbus specification also defines an optional bus clear
(BCLR) signal that is meant to indicate explicitly that the present
master should relinquish the bus. PowerMAXION VME does not
implement this optional signal.
The PowerMAXION computer system provides four options for configuring the bus arbi-
tration: (1) straight priority, (2) round robin, and (3) CPU Release on Request. Combina-
tions of these options are allowed. By default, the system uses the straight slot priority
scheme, whereby the lowest numbered slot that is not occupied by a processor board has
the highest priority.
The bus arbitration schemes are defined by a configuration register that resides within the
VME interface module. This register can be read or written from the processor.
Refer to the VME bus Specification for more information regarding the bus arbitration
scheme.
Interrupt Request Levels and Priorities 6
In the PowerMAXION interrupt architecture, interrupt sources are hardware devices
external to processors, one of the processors or devices attached to the processor, and
software. Possible hardware interrupt sources are device controllers on the I/O bus or the