Specifications

D
evice Driver Programming
6-2
Figure 6-1. Elements of a PowerMAXION Processor Board
Caches 6
There are separate 16-Kbyte, four-way set-associative instruction and data caches. Instruc-
tion cache coherency is maintained in the software; bits in the instruction cache indicate
whether a cache block is valid or not. Four-state data cache coherency (MESI) is main-
CIO
Interface
Error
Add Reg
TOC
PROM
UART
Interval
Timer
Health
Register
EPROM
RTC
Diagnostic
Control
CPU
Register
Error
Register
ID ID
PCI Interface
VME64
VME64
Frontplane
Interface
System
Frontplane
Global
Memory
25MHz Local Bus
Local Bus
Control
Local Memory
Dynamic
PowerPC
604
50MHz Processor Bus
Secondary
Cache
FLASH
Local Memory
Diagnostic
Control
Clock
Ethernet
Interrupt
Controller
SCSI
Interface
Backplane
PCI Bus
VME64 Bus System Bus
System Bus
Generation
Console Bus