Specifications

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Chapter 6PowerMAXION Hardware Environment
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This chapter provides hardware-specific information useful in developing device drivers
for PowerMAXION computer systems.This chapter also explains how hardware configu-
ration affects I/O function and performance.
Some hardware information applies to every driver—for instance, I/O error handling
(affects power failure, alignment errors, controller errors, and bus hangs.) Some informa-
tion differs according to the technique by which the device driver communicates with the
processor—for example, programmed I/O, interrupts, and direct memory access (DMA).
Other information relates as much to software as hardware, such as addressing, byte order-
ing and alignment, word sizes, and configuring arbitration levels and assigning arbitration
priorities.
Communicating with devices via interrupts also poses questions about sharing and config-
uring interrupt levels to ensure adequate performance levels. Finally, other questions arise
when communicating with devices via DMA—for example, cache coherency, buffering
and addressing.
The first part of this chapter introduces the main architectural features of the platform in
terms of its system and I/O architecture: processors, memory and I/O expansion and con-
figuration. The second part examines hardware issues more closely including physical
addressing, I/O bus timeout, configuring I/O interrupt request levels and associated priori-
ties, and assigning interrupt vectors.
System Overview 6
PowerMAXION systems are multiprocessor, real-time, super-microcomputers. They use
Symmetric Superscalar
TM
Reduced Instruction Set Computer (RISC) microprocessors
from IBM/Motorola, the PowerPC 604.
Processor Board 6
Figure 6-1 gives an overview of the main architectural features of the PowerMAXION
processor board. The PowerMAXION computer system can contain up to eight processor
boards. A processor board hosts one processor, secondary cache, local memory module
board, I/O interface, timers, real-time clocks, UART, and so on.
The processor clock speed is either 150 or 200 MHz and is capable of executing four
instructions per cycle. The processor data bus is 64-bit wide to accommodate two-32 bit
instructions per cycle.