Specifications

Power Hawk 610 Hardware Environmen

5-11

If two interrupt requests with the same interrupt level occur simultaneously on the VME

I/O bus, the system resolves the contention by applying the following rules:

1. In devices sharing the same interrupt level on the same I/O bus, the device

with the lowest slot number has the highest priority.

2. In interrupt levels on the same I/O bus, the device connected to level 7 has

the highest priority down to level 1, which has the lowest priority.

3. In all interrupt sources in the system, hardware determines the interrupt

priority of the device by its mapping to the Power Hawk 610 interrupt

levels.

NOTE

For system speed and proper device operation, increase the prior-

ity of devices needing a quick response to interrupts. Decrease the

priority of devices that tolerate longer interrupt latencies; devices

whose interrupts can wait longer before service.

Interrupt Vector Generation and Conﬁguration 5

In hardware, the interrupt process functions as follows:

1. On the VME I/O bus, the interrupt requester requests an interrupt by

driving one of the interrupt request lines (IRQ1* to IRQ7* on the bus)

active low. An interrupt controller that monitors all request lines detects

this.

2. The CPU to which the interrupt controller directed the request generates an

interrupt acknowledge, which the controller returns to the VME device.

3. If necessary, the VME device requests mastership of the bus via arbitration.

4. Once it gains mastership, the system controller generates an interrupt

acknowledge cycle by driving the IACK* signal active low and placing the

winning interrupt level request on the address lines A03 to A01. (The

controller resolved any contention between the interrupt levels.)

5. By a daisy-chain acknowledgment scheme wherein the IACK* signal

propagates via an IACKIN/IACKOUT* signal chain through all I/O bus

slots, the lowest slot number receives the interrupt request

acknowledgment signal IACK* first. The falling edge of the active low on

the IACK* signal validates the data on address lines A03 to A01.

6. Upon detecting its interrupt level code on line A01-A03 on the falling edge

of IACK* low, the interrupt requester identifies itself by placing an

implementation-dependent 8- or 16-bit code on the data lines. The VME-

bus standard calls this the STATUS/ID information code. (The HVME

implementation of the VMEbus standard uses the 8-bit version of the

STATUS/ID information code.)