Specifications

D
evice Driver Programming
5-10
A system can use more than one of these options. By default, the system uses the straight
slot priority scheme, wherein the lowest numbered slot not occupied by a processor board
has the highest priority.
A configuration register in the VME interface module defines the bus arbitration schemes.
The processor can read from or write to this register.
Interrupt Request Levels and Priorities 5
In the Power Hawk 610 interrupts come from both processors or other hardware devices
external to or attached to the processors and software. Sources of hardware interrupts
include:
• Device controllers on the PCI or VME I/O busses
• Powerfail
• 60 Hz clock
• Timers
• Real-time clocks
• Console processor
• Port controllers (serial or parallel.)
Sources of software interrupts include:
• Inter-processor requests
• Softclock
• Context switches.
Interrupt Lines (Levels) 5
On the VME I/O bus, interrupt lines are the bus lines carrying the interrupt signal from
interrupt requester to processor. The VME chassis supports 7 interrupt levels, labeled
IRQ1-7* on the I/O bus.
VME interrupt request lines map to the Power Hawk 610’s interrupt levels, but are not the
only source of interrupts in the system.
Hardware hierarchically and statically sets Interrupt priorities. The hardware interrupt
priority determines the relative urgency of servicing the event within the overall system.
For each interrupt level, the device on the highest interrupt level with the lowest slot
number has the highest priority.
The operating system assigns internal priorities to interrupt levels.