Specifications

Power Hawk 610 Hardware Environmen

5-9

Bus Arbitration 5

Busses that support multiple bus masters must provide a means of resolving the contention

of concurrent requests for bus mastership by multiple devices. This is the purpose of a

special unit on the VME bus, the VME bus arbiter.

Bus arbitration is important only for devices that can act as bus masters. Device

specifications indicate this ability as either “bus master” or “DMA Operation.” Because

bus arbitration depends on implementation, the following sections explain arbitration on

the Power Hawk 610.

Bus Request Levels 5

The VMEbus specification defines extensive bus arbitration options implemented by the

following signals:

• Bus request level BR0

• Bus grant BG0 (BG0IN, BG0OUT)

• Bus busy (BBSY) signal.

Each slot has a BR0xx signal (where xx refers to the slot number) driven to the bus arbiter.

The bus arbiter directly drives a BG0xx signal (where xx refers to the slot number) to the

appropriate slot. This eliminates the latency of daisy chaining the bus grants and can also

configure specific slots for round-robin arbitration. All slots receive the BBSY signal,

when appropriate.

Devices on the VME bus become the bus master by asserting bus request and receiving

bus grant. The new bus master asserts the bus busy (BBSY) signal until relinquishing the

bus. During this time, only it can generate bus addresses.

NOTE

The VMEbus specification defines an optional bus clear (BCLR)

signal for the present master to relinquish the bus. Power Hawk

610 VME does not implement this optional signal.

The Power Hawk 610 VME bus implementation of the VMEbus standard supports all four

bus request levels (for boards that cannot be conﬁgured to BR0/BG0) although BR0/BG0

is recommended whenever possible.

The Power Hawk 610 provides the following options for conﬁguring the bus arbitration:

1. Straight priority

2. Round robin

3. CPU Release on Request.