Specifications

Power Hawk 610 Hardware Environmen
t
5-
7
VME Devices as Bus Masters 5
When a VME device addresses memory (or other VME sources), the VME device is the
bus master.
Table 5-2 shows the address ranges for VME bus master accesses.
Bus Time-Out 5
The VME bus measures with a bus timer the duration of data transfers accessing slave
devices. If a data transfer malfunctions, the bus timer detects the malfunction and
generates a bus time-out, preventing a dead VME slave from hanging the I/O channel.
After a device applies an address to the bus and asserts the address strobe (AS*) and data
strobe (DS*) signals, the VME device addressed must assert the data transfer
acknowledge (DTACK*) signal within 64 microseconds to respond by asserting data
transfer acknowledge (DTACK*). If it does not assert the DTACK* signal in a timely
manner, the VME bus controller asserts bus error (BERR*) and generates a system fault.
Data transfer malfunctions on the bus occur for the following reasons:
• Invalid address
• Invalid address modifier
Table 5-1. VME Bus Slave Access
Address Type Processor Address VME Address
A32 0xC1010000-
0xE0BFFFFF
0xE0010000-
0xFFBFFFFF
A24 0xE0C00000-
0xE0F3FFFF
0xFFC00000-
0xFFF3FFFF
A16 0xC1000000-
0xC100FFFF
0xFFFF0000-
0xFFFFFFFF
Table 5-2. VME Bus Master Access
Transfer Type Address Range Address Type Address Modifier
single 00000000-7FFFFFFF A32 09, 0A, 0D, 0E
block 00000000-7FFFFFFF A32 0B, 0F
block-D64 00000000-7FFFFFFF A32 08,0C
block XX000000-XXBFFFFF A24 39, 3A, 3D, 3E
block-D64 XX000000-XXBFFFFF A24 38,3C
single XX000000-XXBFFFFF A24 39, 3A, 3D, 3E