Specifications

Power Hawk 610 Hardware Environmen
t
5-3
Memory 5
The Power Hawk 610 uses 32-bit addresses for up to four gigabytes of virtual address
space.
Figure 5-1 depicts both the memory provided on the processor card and on an additional
DRAM daughter card. Each location can contain up to 64 MB of dynamic memory for a
total capacity of 128 MB.
Power Hawk DRAM has a non-burst access time of eight 66 Mhz cycles or about 120
nanoseconds. This memory provides no parity or Error Correction (ECC) capability.
Buses 5
The Power Hawk 610 has two main busses: the processor bus and the 32-bit PCI bus.
The processor bus, a dedicated high-performance bus, resides on the processor mezzanine
board. This is supplemented by an industry-standard PCI bus, which is the main bus
connecting the ISA bus and devices, SCSI, Ethernet, and VME interfaces to the processor.
The local ISA bus communicates with the serial and parallel ports, NVRAM, and the
Real-time Clock module; customers cannot access it.
A two-chip set supports the VMEbus; the VME2PCI and the VMEchip2. The VME2PCI
bridge interfaces between the PCI bus and a 68040 local bus. The VMEchip2 provides the
interface between the 68040 local bus and the industry-standard VMEbus. The 68040
local bus exists only as an intermediary between the PCI and VME busses; customers can-
not access it. The VMEbus provides A32 addressing and D64 data transfers, supporting
any third-party controller that can access its addresses.
Timers 5
Several sources provide timers:
• The Intel 82378 ISA Bridge chip contains an interruptible timer providing
the 60 Hz clock interrupt
• The Z8536 multipurpose chip connected to the 82378 contains three 16-bit
timers providing real-time clocks
• The VMEchip2 VMEbus interface chip contains two 32-bit timers provid-
ing real-time clocks.
Interrupts 5
Registers on the ISA Bridge chip provide interrupt priority control. The processor card
routes all interrupts to this chip, which resolves them into one of 16 levels and can