Specifications

D
evice Driver Programming
5-2
Figure 5-1. Elements of a Power Hawk PH610 Processor Board
Caches 5
The processor features separate 16-Kb, four-way set-associative instruction and data
caches. Software maintains instruction cache coherency; bits in the instruction cache flag
whether a cache block is valid. Hardware maintains four-state data cache coherency
(MESI). The processor also supports secondary data cache. Software can disable, lock,
and parity-check caches.
DRAMDRAM ROM BUFFERS
RAM104 PM604 MPU/DRAM MODULE
PowerPC
604
MPC105
PCI
BRIDGE
32-BIT PCI LOCAL BUS
PCI
EXPANSION
PMC SLOT
VME2PCI
VME
VMEchip2
SCSI
NCR-53C825
ETHERNET
DECchip
21040
VGA
CL-GD5434
VIDEO
RAM
ISA
BRIDGE
RTC/
NVRAM
MOUSE
PARALLEL
I/O
FLOPPY DISK
CONTROLLER
(NOT USED)
KEYBOARD
SERIAL
MVME1600-001/011 BASE BOARD