Specifications

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Chapter 5Power Hawk 610 Hardware Environment
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This chapter provides hardware-specific information useful in developing device drivers
for the Power Hawk 610 computer system. This chapter also explains how hardware
configuration affects I/O function and performance.
Some hardware issues are general in nature—for example, I/O error handling (power
failure, alignment errors, controller errors, and bus hangs.) Some information differs
according to the technique by which the device driver communicates with the processor—
for example, programmed I/O, interrupts, and direct memory access (DMA). Other
information relates as much to software as hardware, such as addressing, byte ordering
and alignment, word sizes, and configuring arbitration levels and assigning arbitration
priorities.
Communicating with devices via interrupts also poses questions about sharing and
configuring interrupt levels to ensure adequate performance levels. Finally, other questions
arise when communicating with devices via DMA—for example, cache coherency,
buffering and addressing.
The first part of this chapter introduces the main architectural features of the platform in
terms of its system and I/O architecture: processors, memory and I/O expansion and
configuration. The second part examines hardware issues more closely including physical
addressing, I/O bus timeout, configuring I/O interrupt request levels and associated
priorities, and assigning interrupt vectors.
System Overview 5
Power Hawk 610 systems are uniprocessor, real-time, super-microcomputers. They use
the Symmetric Superscalar
TM
Reduced Instruction Set Computer (RISC) microprocessor
from IBM/Motorola, the PowerPC 604. The processor board is the Motorola MVME1604
Single Board Computer (SBC).
Processor Board 5
Figure 5-1 depicts the main architectural features of the PH610 computer system. A
processor board hosts a single processor, various amounts of memory, an optional L2
cache, I/O interface, various bridge chips, real-time clocks, UART, SCSI interface,
Ethernet interface, and associated components.
The processor cycle time is 10 ns (100 MHz) and can execute four instructions per cycle.
The processor data bus is 64 bits wide to accommodate two 32-bit instructions per cycle.