Specifications

Series 6000 Hardware Environmen
t
4-11
Interrupt Request Levels and Priorities 4
In the Series 6000, interrupts come from both processors or other hardware devices exter-
nal to or attached to the processors and software. Sources of hardware interrupts include:
• Device controllers on the I/O bus
• Powerfail
• 60 Hz clock
• Timers
• Real-time clocks
• Console processor
• Port controllers (serial or parallel.)
Sources of software interrupts include:
• Inter-processor requests
• Softclock
• Context switches.
Interrupt Lines (Levels) 4
On the HVME I/O bus, interrupt lines are the bus lines carrying the interrupt signal from
interrupt requester to processor. The HVME chassis supports 7 interrupt levels, labeled
IRQ1-7* on the I/O bus.
(H)VME interrupt request lines map to the Series 6000 system’s interrupt levels, but are
not the only source of interrupts in the system. For more details and a list of priority levels
and mapping of interrupt sources to those levels, refer to the HN6800 or HN6200 Architec-
ture Manual.
Hardware hierarchically and statically sets Interrupt priorities. The hardware interrupt pri-
ority determines the relative urgency of servicing the event within the overall system. For
each interrupt level, the device on the highest interrupt level with the lowest slot number
has the highest priority.
If two interrupt requests with the same interrupt level occur simultaneously on the HVME
I/O bus, the system resolves the contention by applying the following rules:
1. In devices sharing the same interrupt level on the same I/O bus, the device
with the lowest slot number has the highest priority.
2. In interrupt levels on the same I/O bus, the device connected to level 7 has
the highest priority down to level 1, which has the lowest priority.
3. In all interrupt sources in the system, hardware determines the interrupt pri-
ority of the device by its mapping to the Series 6000 interrupt levels.