Specifications

D
evice Driver Programming
4-10
NOTE
The VMEbus specification defines an optional bus clear (BCLR)
signal for the present master to relinquish the bus. HVME does
not implement this optional signal.
The HVME bus implementation of the VMEbus standard uses only the BR0 bus request
level (for boards that cannot use BR0/BG0, see the following procedure). The bus arbiter
neither uses nor attends to other bus request levels, with the exception of BR3. This bus
request level indicates to Release-On-Request (ROR) devices in the HVME chassis that a
VME request pends in the chassis.
The Series 6000 provides the following options for configuring the bus arbitration:
• Straight priority
• Round robin over processor slots
• Round robin over slots 6 through 11
• CPU Release on Request.
A system can use more than one of these options. By default, the system uses the straight
slot priority scheme, wherein the lowest numbered slot not occupied by a processor board
has the highest priority.
A configuration register in the (H)VME interface module defines the bus arbitration
schemes. The processor can read from or write to this register.
Configuring Devices Without BR0 4
Some devices cannot use BR0 or can only do so by first using another bus request level
such as BR3. To install such a device in the HVME primary I/O bus, use the following
steps:
1. Configure the device to use bus request level BR3.
2. Locate the backplane jumper for the appropriate slot (refer to the system SI
drawing for locations, generally on the rear of the backplane with one
jumper at each slot). This jumper determines whether the board’s BR0 or
BR3 is routed to the bus arbiter.
3. Move the jumper from position 0 to 3. Note that this jumper does not
change the board’s bus request priority in the HVME arbitration scheme.
Refer to the VMEbus Specification and the HVME Extension Specification for more infor-
mation on the bus arbitration scheme.