Specifications

D
evice Driver Programming
4-2
Figure 4-1. Elements of an HN6800 Processor Board
Caches 4
The processor features separate 16-Kb, four-way set-associative instruction and data
caches. Software maintains instruction cache coherency; bits in the instruction cache flag
whether a cache block is valid. Hardware maintains four-state data cache coherency
(MESI). The processor also supports secondary data cache. Software can disable, lock,
and parity-check caches.
CIO
Interface
Local Bus
Error
Add Reg
TOC EPROM UART
Interval
Timer
Health
Register
Interrupt
Controller
RTC
Diagnostic
Control
CPU
Register
Error
Register
ID ID
Port Interface
ISE
Disc
Tape
HVME Interface
HVME Backplane
Frontplane
Interface
System
Frontplane
Bus Watcher
(Snoop Filter)
Global
Memory
Secondary
I/O
Local Bus
Local Bus
Control
Local Memory
50MHz Static
or
50MHz Dynamic
PowerPC
604
604
PowerPC
Processor Bus