Specifications

The PCI Environmen

3-5

ROM Base Address Registers(BAR) 3

Decode into Memory Space 3

Similar to Base Address Registers that decode into Memory Space with the same charac-

teristics. These areas are allocated out of the space set aside for PCI memory space.

Interrupts 3

Each sub function of a PCI device can request one interrupt to be attached to the speciﬁed

Interrupt Pin defined at offset 0x3d. It should be noted that it is highly unlikely that the

Interrupt vector assigned will be exclusive to this device only. Thus all device drivers

must be written with the intent that the vector is shared and it’s respective interrupt handler

will be called at random times with no activity to process.

System Memory and PCI bus Master Devices 3

The entire memory subsystem of PowerPC which can be as large as 2 gigabytes which is

statically mapped into the memory space portion of the PCI bus. This allows the PCI bus

master devices to access the system memory without further intervention by the CPU.

Effects of PCI to PCI Bridges 3

The effects of PCI to PCI bridges on PCI devices it bridges can vary, but generally they

slow down individual read accesses the most. Most PCI bridges have write posting buffers

that allow a couple of writes to be queued in each layer of PCI bus, thus improving the

performance of individual writes to/from PCI devices. These queues are generally ﬂushed

when a read occurs thought the same data path. The effects of PCI bridges on a PCI bus

master is less pronounced since they generally move more data per PCI arbitration timing

slot. Where most of overhead by PCI bridges is in the setup and the ﬁrst access. To reduce

this effect even further the programmer should maximize the Bus mastering burst size to

the largest the device can accommodate within reason. This value is generally of the total

DMA FIFO size.

PowerMax OS Support 3

Each PCI device and sub function are assigned a adapter structure entry at System IPL

time. Normally the sub functions of each PCI device should be treated as separate

devices. I.E. SCSI and Ethernet functions combined on a single chip. However their are

exceptions and a single driver may manipulate multiple functions, for that case it should

be noted that all the sub functions will be clustered together in a serial fashion in the

adapter array.