Specifications

Motorola MCP750 Hardware Environmen
t
8-5
- The PCI bus (interrupts from PCI devices)
- The CPCI bus (interrupts from CPCI devices)
- Power monitor interrupts
- Watchdog timer interrupt
- The ISA bus (interrupts from ISA devices)
Some of the features of the Raven ASIC include:
Support for 16 external interrupts
Support for 15 programmable Interrupt & Processor Task priority levels
Support for the connection of an external 8259 for ISA/AT compatibility
Distributed interrupt delivery for external I/O interrupts
Direct/Multicast interrupt delivery for Interprocessor and timer interrupts
Four Interprocessor Interrupt sources
Four timers
Processor initialization control
Four 31 bit interrupting tick timers for periodic interrupt generation.
DATA TYPES 8
The Motorola MCP750 supports the following data types:
- Byte (8 bits)
- Half-Word (16 bits)
- Word (32 bits)
- Doubleword (64 bits)
BYTE-ORDERING AND ALIGNMENT 8
Byte-Ordering and Alignment 8
The byte-ordering convention used in the Motorola MCP750 platform is Big Endian.In
this model, the most significant byte (MSB) always has the lowest address. This provides a
consistency of addressing which is independent of the word size of the machine. See