Specifications

D
evice Driver Programming
8-4
BUSSES 8
There are two main busses on the MCP750, the processor bus (also called the MPC60X
bus) and the 64-bit PCI bus.
Interfacing with the processor bus is the MPC750 processor with external cache, the Fal-
con chipset and the Raven.
The Raven supplies the host bridge interface to the primary PCI bus. Interfacing with the
primary PCI bus is a PMC slot, a PCI-to-PCI bridge supporting the compact PCI back-
plane, a PCI-to-ISA/IDE/USB bridge, Ethernet, and one PMC slot.
The primary PCI bus has the following attributes:
- high performance 32-bit or 64-bit,
- burst mode,
- synchronous bus capable of transfer rates of 132 MByte/sec in 32-bit mode
or 264 MByte/sec in 64-bit mode,
- a 33 MHz clock
TIMERS 8
The M48T559, real time clock part, provides the MCP750 a time-of-day clock and a
watchdog timer.
The Raven ASIC supports four 31 bit tick timers and two watchdog timers. The four dec-
rementing timers may be used for system timing or to generate periodic interrupts.
The two watchdog timers are designed to be reloaded by software at any time. When not
being loaded, the timer will continuously decrement itself until either reloaded by soft-
ware or a count of zero is reached. If a timer reaches a count of zero, an output signal will
be asserted and the count will remain at zero until reloaded by software or Raven s reset is
asserted. External logic can use the output signals of the timers to generate interrupts,
machine checks, etc.
INTERRUPTS 8
The Raven ASIC supplies the MCP750 with an MPIC compliant interrupt controller to
handle various interrupt sources. Sources of interrupts may be any of the following:
- The Raven ASIC itself (timer interrupts or transfer error interrupts)
- The processor 0(processor self-interrupts)
- The Falcon chip set (memory error interrupts)