Specifications

D
evice Driver Programming
8-2
The MCP750 provides the 1 MB backdoor external cache option. The Falcon chip set con-
trols the boot Flash and the ECC DRAM. The Raven ASIC functions as the 64-bit PCI
host bridge and the MPIC interrupt controller. PCI devices include: Ethernet, a PCI-to-PCI
bridge for
CompactPCI bus interface (optional second bridge located on companion card), a PCI-to-
ISA/IDE/USB bridge, and one PMC slot. Standard I/O functions (serial, parallel, FDD,
and keyboard) are provided by the Super I/O device which resides on the ISA bus. The
NVRAM/RTC provides NVRAM and an RTC with battery backup. A 512 x 8 Serial
EEPROM is also provided via an I2C interface off of the PBC.
Refer to Figure 8-1 for a block diagram representation of these features.
MEMORY 8
The Falcon DRAM controller ASIC is designed for the PowerPC families of boards. It is
used in sets of two to provide the interface between the PowerPC 60x bus (also called
MPC60x bus or MPC bus) and a 144-bit ECC-DRAM memory system. It also provides an
interface to ROM/Flash.
The Falcon chipset supports up to 256MB of ECC DRAM with the following features:
- Double-bit error detect/Single-bit error correct on 72-bit basis.
- Up to four blocks.
- Programmable base address for each block.
- Two-way interleave factor.
- Built-in Refresh/Scrub.
- Software programmable Interrupt on Single/Double-Bit Error.
- Error address and Syndrome Log Registers for Error Logging.
- Does not provide TEA_ on Double-Bit Error. (Chip has no TEA_ pin.)
The Falcon pair provides the interface for two blocks of ROM/Flash. Each block provides
addressing and control for up to 64Mbytes. The ROM/Flash interface provides:
- Two blocks with each block being 16 bits wide (8 bits per Falcon), or 64
bits wide (32 bits per Falcon).
- Software programmable access time for each block.
- No ECC error checking is provided for the ROM/Flash.