Specifications

D
evice Driver Programming
7-12
VME interrupt request lines are only one source of interrupts in the system. VME
interrupt request lines are mapped to the Power Hawk 620/640 system’s interrupt levels.
For additional details and a list of priority levels and the mapping of interrupt sources to
these levels, refer to either the Motorola MVME 2600 Architecture Manual or the
Motorola MVME 4600 Architecture Manual.
Following are some additional characteristics of the Power Hawk 620/640 interrupt levels.
The hardware interrupt priority determines the relative urgency of servicing the event
within the overall system.
Interrupt priorities are set hierarchically and statically in hardware. For each interrupt
level, the device on the highest interrupt level with the lowest slot number has the highest
priority.
If two interrupt requests occur on the same interrupt level simultaneously on the VME I/O
bus, the system resolves the contention as follows:
1. Among devices sharing the same interrupt level on the same I/O bus, the
device with the lowest slot number has the highest priority.
2. Among interrupt levels on the same I/O bus, the device connected to level 7
has the highest priority down to level 1, which has the lowest priority.
3. Among all interrupt sources in the system, the interrupt priority of the
device is predetermined in hardware by its mapping to the Power Hawk
620/640 interrupt levels.
NOTE
For system performance and proper device operation, if a device
is time-critical in that it expects response to an interrupt to be
quick, it should be moved to a higher priority. Devices that can
tolerate longer interrupt latencies—that is, devices whose
interrupts can wait for a longer time before being serviced—
should be assigned to a lower priority.
Interrupt Vector Generation and Configuration 7
In hardware, the interrupt process functions as follows. On the VME I/O bus, the interrupt
requester requests an interrupt by driving one of the interrupt request lines (IRQ1* to
IRQ7* on the bus) active low. This is detected by an interrupt controller that monitors all
request lines. The interrupt acknowledge is generated by the CPU to which the request has
been directed to by the interrupt controller. The acknowledge then is passed by the
controller to the VME. The VME, in turn, requests mastership of the bus via arbitration if
necessary.
Once it gains mastership, the system controller generates an interrupt acknowledge cycle
by driving the IACK* signal active low and placing the winning interrupt level request on
the address lines A03 to A01. Note that at this point, the controller has resolved any
contention between the interrupt levels. By a daisy-chain acknowledgment scheme