Specifications

Power Hawk 620/640 Hardware Environmen
t
7-11
Bus arbitration is important only for devices that can act as bus masters. This is indicated
in a device specification as either “bus master” or “DMA Operation.” Because bus
arbitration is implementation-dependent, the following explains what you need to know
about arbitration on the Power Hawk 620/640 systems.
Bus Request Levels 7
The VMEbus specification defines extensive bus arbitration options. The options are
implemented using a bus request level BR0, a bus grant BG0 (BG0IN, BG0OUT), and a
bus busy (BBSY) signal. Each slot has a BR0xx signal (where xx refers to the slot number)
driven to the bus arbiter. The bus arbiter directly drives a BG0xx signal (where xx refers to
the slot number) to the appropriate slot. This eliminates the latency of daisy chaining the
bus grants and also allows specific slots to be configured for round-robin arbitration.
BBSY is bussed to all slots.
A device on the VME bus becomes the bus master by asserting bus request and receiving
bus grant. The new bus master then asserts the bus busy (BBSY) signal until it is ready to
relinquish the bus. During this time, the device is the only one allowed to generate bus
addresses until it releases the bus.
The Power Hawk 620/640 implementation of the VMEbus standard supports all four of
the bus request levels although BR0/BG0 is recommended whenever possible.
The Power Hawk 620/640 provides two options for configuring the bus arbitration: (1)
straight priority and (2) CPU Release on Request. Combinations of these options are
allowed. By default, the system uses the straight slot priority scheme, whereby the lowest
numbered slot that is not occupied by a processor board has the highest priority.
The bus arbitration schemes are defined by a configuration register that resides within the
VME interface module. This register can be read or written from the processor. Refer to
the VME bus Specification for more information regarding the bus arbitration scheme.
Interrupt Request Levels and Priorities 7
In the Power Hawk 620/640 interrupt architecture, interrupt sources are hardware devices
external to processors, one of the processors or devices attached to the processor, and
software. Possible hardware interrupt sources are device controllers on the PCI or VME
I/O bus or the powerfail, 60 Hz clock, timers, real-time clocks, the console processor,
serial or parallel port controllers, and so on. Software interrupt sources include inter-
processor interrupts, the softclock interrupt, and context switch interrupts.
Interrupt Lines (Levels) 7
On the VME I/O bus, the bus lines carrying the interrupt signal from an interrupt requester
to a processor are called interrupt lines. The VME chassis supports 7 interrupt levels. On
the I/O bus, these are labeled IRQ1-7*.