Specifications

Power Hawk 620/640 Hardware Environmen
t
7-9
Bus Time-Out 7
For each data transfer accessing a slave device, the VME bus provides a bus timer which
measures the duration of the transfer. If the data transfer malfunctions, the bus timer unit
detects the condition and generates a bus time-out to avoid having a dead VME slave hang
the I/O channel.
Here are some details on the bus timeout mechanism. After an address is applied to the bus
and the address strobe (AS*) signal is asserted, a VME device has 51.2 microseconds to
respond by asserting data transfer acknowledge (DTACK*). If this timing is not met, the
VME bus controller asserts bus error (BERR*) and generates a system fault.
A data transfer malfunction occurs when using an invalid address, address modifier, or
transfer on the bus. Another possibility is that the device being addressed does not exist or
malfunctions.
The kernel normally recognizes VME bus errors and determines, to some extent, the
reason for the error. In most cases, the next action taken by the kernel is to panic the
system. A panic allows for a fix to be made to a board or device, or for some other action
to be taken. However, in some cases, such as a particular real-time or production mode
environment, panicking the system might not be the most desirable way to handle the bus
error.
The iobus_err(2) system service can provide an alternative method for handling
some types of VME bus errors, without panicking the system. See Chapter 16, “Special
Table 7-2. VME Bus Master Access
Address Type Address Transfer Type Address Modifier
A32: Start
End
00000000
7FFFFFFF
single 09, 0A, 0D, 0E
A32: Start
End
00000000
7FFFFFFF
block 0B, 0F
A32: Start
End
00000000
7FFFFFFF
block-D64 08, 0C
A24: Start
End
XX000000
XXBFFFFF
block 39, 3A, 3D, 3E
A24: Start
End
XX000000
XXBFFFFF
block-D64 38, 3C
A24: Start
End
XX000000
XXBFFFFF
single 39, 3A, 3D, 3E