MC68VZ328 Integrated Processor User's Manual

Programming Model
 System Control 5-5
5.2.3 ID Register
This 32-bit read-only register shows the chip identification. The bit assignments for the register are shown
in the following register display. The settings for the bits in the register are listed in Table 5-3.
IDR ID Register 0x(FF)FFF004
BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 BIT 16
CHIPID MASKID
TYPEr r r r r r rrrrrrrrr r
RESET
0 1 0 1 0 1 100000000 0
0x5600
BIT 1514 13 12 11 10 987654321BIT 0
SWID
TYPEr r r r r r rrrrrrrrr r
RESET
0 0 0 0 0 0 000000000 0
0x0000
Table 5-3. ID Register Description
Name Description Setting
CHIPID
Bits 31–24
Chip ID Field—This field contains the chip identification number for the
DragonBall series MPU.
See description
MASKID
Bits 23–16
Maskset ID Field—This field contains the maskset number for the silicon. See description
SWID
Bits 15–0
Software ID—This field contains the custom software ID. It is normally “0000.” See description