MC68VZ328 Integrated Processor User's Manual

19-30 MC68VZ328 User’s Manual 
AC Electrical Characteristics
19.3.25 Page-Hit LCD DMA Cycle for SDRAM (CAS
Latency = 1)
Figure 19-26 shows the timing diagram for the page-hit LCD DMA cycle for SDRAM. The signal values
and units of measure for this figure are found in Table 19-16 on page 19-31. Detailed information about
the operation of individual signals can be found in both Chapter 8, “LCD Controller,” and Chapter 7,
“DRAM Controller.”
Figure 19-26. Page-Hit LCD DMA Cycle for SDRAM Timing Diagram
SDCLK
RAS
SCKEN
D[15:0]
CAS
A[16:1]/MD[15:0]
SDA10
CS
WE
DQM
DTACK
Read
Command
Read
Command
Read
Command
Read
Command
Col n Col n+1 Col n+2 Col n+3
Data n Data n+1 Data n+2 Data n+3