MC68VZ328 Integrated Processor User's Manual

19-20 MC68VZ328 User’s Manual 

AC Electrical Characteristics

19.3.15 Page-Hit SDRAM CPU Read Cycle (CAS Latency = 1)

Figure 19-16 shows the timing diagram for the page-hit SDRAM CPU read cycle. The signal values and

units of measure for this figure are found in Table 19-16 on page 19-31. Detailed information about the

operation of individual signals can be found in both Chapter 8, “LCD Controller,” and Chapter 7, “DRAM

Controller.”

Figure 19-16. Page-Hit SDRAM CPU Read Cycle Timing Diagram

S0 S2 S4 S4 S6 S7S5S4S3S1

SDCLK

RAS

SCKEN

D[15:0]

CAS

A[16:1]/MD[15:0]

SDA10

DQM

DTACK

Read

Command

Col