MC68VZ328 Integrated Processor User's Manual

AC Electrical Characteristics
 Electrical Characteristics 19-15
Table 19-13. LCD DRAM DMA Cycle 16-Bit EDO RAM Mode Access (LCD Bus Master)
Timing Parameters
Number Characteristic
(3.0 ± 0.3) V
Unit
Minimum Maximum
1 Row address valid to RASx
asserted 45 —ns
2DWE
negated before row address valid 0 — ns
3OE
asserted before RASx asserted 0 — ns
4 RASx
asserted before row address invalid
(MSW = 0,1)
12,27 — ns
5 Column address valid to CASx
asserted
(MSW = 0,1)
10,25 — ns
6 RASx asserted to CASx asserted (MSW = 0,1) 28,58 — ns
7 CASx
asserted to data-in valid — 20 ns
8 CASx
asserted before column address invalid 20 — ns
9 RASX
pulse width (2N + 1)T — ns
10 CASx
pulse width 28 — ns
11 CASx
precharge time 26 — ns
12 RASx
negated to CASx negated -28 — ns
13 Data-in hold after CASx
negated 30 — ns
14 OE
negated after CASx negated 28 32 ns
Note:
N is the number of words in one DMA transfer.
T is the system clock period.
RASx stands for RAS0 and RAS1. CASx stands for CAS0 and CAS1.
MSW is bit 5 in the DRAMC register. When this bit is set to 0, the first timing number applies; when it is set to 1, the
second timing number applies.