MC68VZ328 Integrated Processor User's Manual

AC Electrical Characteristics
 Electrical Characteristics 19-9
Figure 19-6. DRAM Read Cycle 16-Bit Access (CPU Bus Master) Timing Diagram
Table 19-8. DRAM Read Cycle 16-Bit Access (CPU Bus Master) Timing Parameters
Number Characteristic
(3.0 ± 0.3) V
Unit
Minimum Maximum
1 Row address valid to RASx
asserted 40 —ns
2DWE
negated before row address valid 0 — ns
3OE
asserted before RASx is asserted 0 — ns
4 RASx
asserted before row address invalid
(MSW = 0,1)
12,27 — ns
5 Column address valid to CASx asserted
(MSW = 0,1)
10,25 — ns
6 RASx
asserted to CASx asserted
(MSW = 0,1)
28,58 32 ns
7 RASx pulse width (SLW = 0,1) 90,120 — ns
8 CASx
pulse width (BC[1:0] = 00,01,10,11) 28,58,88,118 — ns
9 CASx
asserted to data-in valid
(BC[1:0] = 00,01,10,11 for FPM)
— 15,45,75,105 (FPM)
20 (EDO)
ns
10 Data-in hold after CASx is negated 0 (FPM)
30 (EDO)
—ns
11 OE
negated after CASx is negated 0 (FPM)
30 (EDO)
35 ns
MD[12:0]
RASx
CASx
DWE
D[15:0]
1
4
5
12
6 8 13
7
3
2
11
9 10
OE
ColumnRow Row
14