MC68VZ328 Integrated Processor User's Manual

Programming Model
 Universal Asynchronous Receiver/Transmitter 1 and 2 14-29
14.4.14 FIFO Level Marker Interrupt Register
The UART FIFO level marker register configures the level at which either the RxFIFO or the TxFIFO
reports a half-full condition. The bit position assignments for this register are shown in the following
register display. The settings for this register are described in Table 14-16.
HMARK FIFO Level Marker Interrupt Register 0x(FF)FFF91C
BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 BIT 0
TXFIFO LEVEL MARKER RXFIFO LEVEL MARKER
TYPE
rw rw rw rw rw rw rw rw
RESET
0 000000100000010
0x0102
Table 14-16. FIFO Level Marker Interrupt Register Description
Name Description Setting
Reserved
Bits 15–12
Reserved These bits are reserved and should
be set to 0.
TXFIFO
LEVEL
MARKER
Bits 11–8
TxFIFO Level Marker—This field defines the level at which
the TxFIFO marker is set. When the TxFIFO status matches
the level marker selected here, the TxFIFO half status bit is set
and the TXFIFO HALF interrupt is generated if it is enabled.
See Table 14-17 on page 14-30 for
settings.
Reserved
Bits 7–4
Reserved These bits are reserved and should
be set to 0.
RXFIFO
LEVEL
MARKER
Bits 3–0
RxFIFO Level Marker—This field defines the level at which
the RxFIFO marker is set. When the RxFIFO status matches
the level marker selected here, the RxFIFO half status bit is
set and the RXFIFO HALF interrupt is generated if it is
enabled.
See Table 14-17 on page 14-30 for
settings.