MC68VZ328 Integrated Processor User's Manual

Programming Model
 Real-Time Clock 11-13
RTCIENR RTC Interrupt Enable Register 0x(ff)FFFB10
BIT
15
14 13 12 11 10 9 8 7 6 5 4 3 2 1
BIT
0
RIE7 RIE6 RIE5 RIE4 RIE3 RIE2 RIE1 RIE0 HR 1HZ DAY ALM MIN SW
TYPE rw rw rw rw rw rw rw rw rw rw rw rw rw rw
RESET
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0x0000
Table 11-10. RTC Interrupt Enable Register Description
Name Description Setting
RIE7
Bit 15
Real-Time Interrupt Enable Bit 7—This bit enables the
real-time interrupt 7. The frequency of this interrupt is
shown in Table 11-9 on page 11-12.
0 = RIE7 interrupt is disabled.
1 = RFE7 interrupt is enabled.
RIE6
Bit 14
Real-Time Interrupt Enable Bit 6—This bit enables the
real-time interrupt 6. The frequency of this interrupt is
shown in Table 11-9 on page 11-12.
0 = RIE6 interrupt is disabled.
1 = RIE6 interrupt is enabled.
RIE5
Bit 13
Real-Time Interrupt Enable Bit 5—This bit enables the
real-time interrupt 5. The frequency of this interrupt is
shown in Table 11-9 on page 11-12.
0 = RIE5 interrupt is disabled.
1 = RIE5 interrupt is enabled.
RIE4
Bit 12
Real-Time Interrupt Enable Bit 4—This bit enables the
real-time interrupt 4. The frequency of this interrupt is
shown in Table 11-9 on page 11-12.
0 = RIE4 interrupt is disabled.
1 = RIE4 interrupt is enabled.
RIE3
Bit 11
Real-Time Interrupt Enable Bit 3—This bit enables the
real-time interrupt 3. The frequency of this interrupt is
shown in Table 11-9 on page 11-12.
0 = RIE3 interrupt is disabled.
1 = RIE3 interrupt is enabled.
RIE2
Bit 10
Real-Time Interrupt Enable Bit 2—This bit enables the
real-time interrupt 2. The frequency of this interrupt is
shown in Table 11-9 on page 11-12.
0 = RIE2 interrupt is disabled.
1 = RIE2 interrupt is enabled.
RIE1
Bit 9
Real-Time Interrupt Enable Bit 1—This bit enables the
real-time interrupt 1. The frequency of this interrupt is
shown in Table 11-9 on page 11-12.
0 = RIE1 interrupt is disabled.
1 = RIE1 interrupt is enabled.
RIE0
Bit 8
Real-Time Interrupt Enable Bit 0—This bit enables the
real-time interrupt 0. The frequency of this interrupt is
shown in Table 11-9 on page 11-12.
0 = RIE0 interrupt is disabled.
1 = RIE0 interrupt is enabled.
Reserved
Bits 7–6
Reserved These bits are reserved and should
be set to 0.
HR
Bit 5
Hour Flag—This bit enables interrupts occurring at a
one-per-hour rate.
0 = 1-hour interrupt disabled.
1 = 1-hour interrupt enabled.
1HZ
Bit 4
1 Hz Flag—This bit enables interrupts occurring at a
1 Hz rate.
0 = 1 Hz interrupt disabled.
1 = 1 Hz interrupt enabled.
DAY
Bit 3
Day Interrupt Enable—This bit enables the day inter-
rupt occurring at a midnight rollover (0000 hours) of the
day counter.
0 = 24-hour rollover interrupt is
disabled.
1 = 24-hour rollover interrupt is
enabled.