MC68VZ328 Integrated Processor User’s Manual MC68VZ328UM/D Rev.
MFAX and DragonBall are trademarks of Motorola, Inc. This document contains information on a new product. Specifications and information herein are subject to change without notice. Motorola reserves the right to make changes without further notice to any products herein.
Contents About This Book Audience . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xxvii Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xxvii Suggested Reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xxix Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.7 2.8 2.9 2.10 2.11 2.12 2.13 2.14 2.15 2.16 Interrupt Controller Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6 LCD Controller Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7 UART 1 and UART 2 Controller Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8 Timer Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
.2.2 5.2.3 5.2.4 Peripheral Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4 ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5 I/O Drive Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6 Chapter 6 Chip-Select Logic 6.1 6.2 6.2.1 6.2.2 6.2.3 6.3 6.3.1 6.3.2 6.3.3 6.3.4 6.3.5 6.3.6 6.3.7 Overview of the CSL . . .
8.2.2.1 Format of the LCD Screen . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-4 8.2.2.2 Format of the Cursor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-5 8.2.2.3 Mapping the Display Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-6 8.2.2.4 Generating Grayscale Tones . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-6 8.2.3 Using Low-Power Mode. . .
9.6.3 9.6.4 9.6.5 9.6.6 9.7 9.8 Interrupt Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupt Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupt Pending Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupt Level Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Keyboard Interrupts .
10.4.6 10.4.6.1 10.4.6.2 10.4.6.3 10.4.6.4 10.4.6.5 10.4.7 10.4.7.1 10.4.7.2 10.4.7.3 10.4.7.4 10.4.7.5 10.4.8 10.4.8.1 10.4.8.2 10.4.8.3 10.4.8.4 10.4.8.5 10.4.8.6 10.4.9 10.4.9.1 10.4.9.2 10.4.9.3 10.4.9.4 10.4.9.5 10.4.10 10.4.10.1 10.4.10.2 10.4.10.3 10.4.10.4 10.4.10.5 10.4.11 10.4.11.1 10.4.11.2 10.4.11.3 10.4.11.4 10.4.11.5 Port E Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port E Direction Register . . . . . . . . . . . . . . . . . .
11.1.6.1 Minute Stopwatch Application Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-4 11.2 Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-5 11.2.1 RTC Time Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-5 11.2.2 RTC Day Count Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-6 11.2.
13.4 SPI 2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.5 SPI 2 Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.5.1 SPI 2 Phase and Polarity Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.5.2 SPI 2 Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.
15.2 PWM 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-2 15.3 PWM Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-3 15.3.1 Playback Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-3 15.3.1.1 Tone Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
17.1.3 Setting Up the RS-232 Terminal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17.1.4 Changing the Speed of Communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17.1.5 System Initialization Programming Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17.1.6 Application Programming Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17.1.7 Example of Instruction Buffer Usage . . . . . . . . . . . . . .
19.3.23 19.3.24 19.3.25 19.3.26 19.3.27 19.3.28 19.3.29 19.3.30 19.3.31 19.3.32 19.3.33 19.3.34 Page-Miss at Starting of LCD DMA for SDRAM (CAS Latency = 1) . . . . . . . . Page-Miss at Start and in Middle of LCD DMA (CAS Latency = 1) . . . . . . . . . Page-Hit LCD DMA Cycle for SDRAM (CAS Latency = 1) . . . . . . . . . . . . . . . SPI 1 and SPI 2 Generic Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SPI 1 Master Using DATA_READY Edge Trigger . . . . . . . . . . . . . .
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List of Figures Figure 1-1 Figure 1-2 Figure 1-3 Figure 2-1 Figure 2-2 Figure 3-1 Figure 4-1 Figure 4-2 Figure 4-3 Figure 4-4 Figure 4-5 Figure 6-1 Figure 7-1 Figure 7-2 Figure 7-3 Figure 8-1 Figure 8-2 Figure 8-3 Figure 8-4 Figure 9-1 Figure 10-1 Figure 10-2 Figure 10-3 Figure 11-1 Figure 12-1 Figure 12-2 Figure 13-1 Figure 13-2 Figure 13-3 Figure 13-4 Figure 14-1 Figure 14-2 Figure 14-3 Figure 14-4 MC68VZ328 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 15-1 Figure 15-2 Figure 15-3 Figure 15-4 Figure 16-1 Figure 16-2 Figure 16-3 Figure 16-4 Figure 17-1 Figure 17-2 Figure 19-1 Figure 19-2 Figure 19-3 Figure 19-4 Figure 19-5 Figure 19-6 Figure 19-7 Figure 19-8 Figure 19-9 Figure 19-10 Figure 19-11 Figure 19-12 Figure 19-13 Figure 19-14 Figure 19-15 Figure 19-16 Figure 19-17 Figure 19-18 Figure 19-19 Figure 19-20 Figure 19-21 Figure 19-22 Figure 19-23 Figure 19-24 Figure 19-25 Figure 19-26 Figure 19-27 xvi PWM 1 and PWM 2 System Configuration Diagram
Figure 19-28 Figure 19-29 Figure 19-30 Figure 19-31 Figure 19-32 Figure 19-33 Figure 19-34 Figure 19-35 Figure 20-1 Figure 20-2 Figure 20-3 Figure 20-4 SPI 1 Master Using DATA_READY Edge Trigger Timing Diagram . . . . . . 19-32 SPI 1 Master Using DATA_READY Level Trigger Timing Diagram . . . . . 19-33 SPI 1 Master “Don’t Care” DATA_READY Timing Diagram . . . . . . . . . . . 19-33 SPI 1 Slave FIFO Advanced by Bit Count Timing Diagram . . . . . . . . . . . . .
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List of Tables Table 1-1 Table 1-2 Table 2-1 Table 3-1 Table 3-2 Table 4-1 Table 4-2 Table 4-3 Table 4-4 Table 4-5 Table 5-1 Table 5-2 Table 5-3 Table 5-4 Table 6-1 Table 6-2 Table 6-3 Table 6-4 Table 6-5 Table 6-6 Table 6-7 Table 6-8 Table 6-9 Table 6-10 Table 6-11 Table 6-12 Table 6-13 Table 6-14 Table 7-1 Table 7-2 Table 7-3 Table 7-4 Table 7-5 Table 7-6 Address Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6 Instruction Set . . . . . . . . .
Table 7-7 Table 7-8 Table 7-9 Table 7-10 Table 8-1 Table 8-2 Table 8-3 Table 8-4 Table 8-5 Table 8-6 Table 8-7 Table 8-8 Table 8-9 Table 8-10 Table 8-11 Table 8-12 Table 8-13 Table 8-14 Table 8-15 Table 8-16 Table 8-17 Table 8-18 Table 8-19 Table 8-20 Table 9-1 Table 9-2 Table 9-3 Table 9-4 Table 9-5 Table 9-6 Table 9-7 Table 9-8 Table 10-1 Table 10-2 Table 10-3 Table 10-4 Table 10-5 Table 10-6 Table 10-7 xx DRAM Control Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 10-8 Table 10-9 Table 10-10 Table 10-11 Table 10-12 Table 10-13 Table 10-14 Table 10-15 Table 10-16 Table 10-17 Table 10-18 Table 10-19 Table 10-20 Table 10-21 Table 10-22 Table 10-23 Table 10-24 Table 10-25 Table 10-26 Table 10-27 Table 10-28 Table 10-29 Table 10-30 Table 10-31 Table 10-32 Table 10-33 Table 10-34 Table 10-35 Table 10-36 Table 10-37 Table 10-38 Table 10-39 Table 10-40 Table 10-41 Table 10-42 Table 10-43 Table 10-44 Table 10-45 Table 10-46 Port B Data Register Description . . . . . .
Table 10-47 Table 10-48 Table 10-49 Table 10-50 Table 10-51 Table 10-52 Table 10-53 Table 10-54 Table 10-55 Table 11-1 Table 11-2 Table 11-3 Table 11-4 Table 11-5 Table 11-6 Table 11-7 Table 11-8 Table 11-9 Table 11-10 Table 11-11 Table 12-1 Table 12-2 Table 12-3 Table 12-4 Table 12-5 Table 12-6 Table 12-7 Table 13-1 Table 13-2 Table 13-3 Table 13-4 Table 13-5 Table 13-6 Table 13-7 Table 13-8 Table 14-1 Table 14-2 Table 14-3 Table 14-4 xxii Port K Data Register Description . . . . . . . . . . . . . . . .
Table 14-5 Table 14-6 Table 14-7 Table 14-8 Table 14-9 Table 14-10 Table 14-11 Table 14-12 Table 14-13 Table 14-14 Table 14-15 Table 14-16 Table 14-17 Table 15-1 Table 15-2 Table 15-3 Table 15-4 Table 15-5 Table 15-6 Table 15-7 Table 15-8 Table 16-1 Table 16-2 Table 16-3 Table 16-4 Table 16-5 Table 16-6 Table 17-1 Table 19-1 Table 19-2 Table 19-3 Table 19-4 Table 19-5 Table 19-6 Table 19-7 Table 19-8 Table 19-9 Table 19-10 Table 19-11 UART 1 Baud Control Register Description . . . . . . . . . . . . . . . .
Table 19-12 Table 19-13 Table 19-14 Table 19-15 Table 19-16 Table 19-17 Table 19-18 Table 20-1 xxiv LCD SRAM/ROM DMA Cycle 16-Bit Mode Access Timing Parameters . . 19-14 LCD DRAM DMA Cycle 16-Bit EDO RAM Mode Access (LCD Bus Master) Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-15 LCD DRAM DMA Cycle 16-Bit Fast Page Mode Access (LCD Bus Master) Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
List of Examples Example 4-1 Example 4-2 Example 6-1 Example 6-2 Example 7-1 Example 8-1 Example 14-1 Example 17-1 Example 17-2 Example 17-3 Configuring the PLLCLK Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7 Shutdown Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-12 Unprotected Memory Size Calculation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-18 Programming Example . . . . . . . . . . . . . . . .
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About This Book This user’s manual describes the features and operation of the MC68VZ328 (DragonBall™ VZ) microprocessor, the third generation of the DragonBall family of products. It provides the details of how to initialize, configure, and program the MC68VZ328. The manual presumes basic knowledge of 68000 architecture. Audience The MC68VZ328 user’s manual is intended to provide a design engineer with the necessary data to successfully integrate the MC68VZ328 into a wide variety of applications.
Chapter 9 Interrupt Controller: This chapter provides a description and operational considerations for interrupt controller operation. It includes a description of the vector generator and pen and keyboard interrupts. Chapter 10 I/O Ports: This chapter covers all 76 GPIO lines found in the MC68VZ328. Because each pin is individually configurable, a detailed description of the operation of and programming information for each pin is provided.
Suggested Reading The following documents are required for a complete description of the MC68VZ328 and are necessary to design properly with the part. Especially for those not familiar with the 68000 CPU, the following documents will be helpful when used in conjunction with this manual.
Definitions, Acronyms, and Abbreviations The following list defines the acronyms and abbreviations used in this document.
Chapter 1 Introduction This chapter describes the overall system architecture of the MC68VZ328 (DragonBall™ VZ) integrated processor. It provides an overview of the 68000 CPU and the operational blocks of the MC68VZ328 at a system level. The MC68VZ328 builds on the success of the earlier DragonBall processors and features a synthesizable 68000 core that utilizes an advanced process technology.
Features of the MC68VZ328 CGM & Power Control Real-Time Clock In-Circuit Emulation Interrupt Controller Memory Controller Bootstrap Mode 8/16-Bit 68000 Bus Interface SPI 1 SPI 2 16-Bit PWM 2 UART 1 with IrDA1.0 8-Bit PWM 1 UART 2 with IrDA1.0 GPIO Ports 16-Bit Timers (2) LCD Controller 68000 Internal Bus GPIO Ports FLX68000 Static CPU Figure 1-1. MC68VZ328 Block Diagram 1.
Features of the MC68VZ328 — Five general-purpose, programmable edge/level/polarity interrupt IRQs — Other programmable I/O, multiplexed with peripheral functions of up to 76 GPIO lines — Programmable interrupt vector response for on-chip peripheral modules — Low-power mode control • DRAM controller — Support for CAS-before-RAS refresh cycles and self-refresh mode DRAM — Support for 8-bit and 16-bit port DRAM and synchronous DRAM — EDO RAM or automatic Fast Page Mode for LCD access — Programmable refresh r
CPU • Built-in emulation function — Dedicated memory space for emulator debug monitor with chip-select — Dedicated interrupt (interrupt level 7) for in-circuit emulation (ICE) — One address-signal comparator and one control-signal comparator, with masking to support single or multiple hardware execution — Breakpoint — One breakpoint instruction insertion unit • Bootstrap mode function — Capability to initialize system and download programs and data to system memory through UART — Acceptance of execution
CPU 1.2.1 CPU Programming Model The CPU has 32-bit registers and a 32-bit program counter, which are shown in Figure 1-2. The first eight registers (D7–D0) are data registers that are used for byte (8-bit), word (16-bit), and long-word (32-bit) operations. When being used to manipulate data, the data registers affect the status register (SR). The next seven registers (A6–A0) and the user stack pointer (USP) can function as software stack pointers and base address registers.
CPU 1.2.2 Data and Address Mode Types The CPU supports five types of data and six main types of address modes. The five types of data are bits, binary-coded decimal (BCD) digits, bytes, words, and long words. The six types of address modes are shown in Table 1-1. Table 1-1. Address Modes Address Mode Register direct address • Data register direct • Address register direct Absolute data address • Absolute short • Absolute long Syntax Dn An xxx.W xxx.
CPU Table 1-2.
Modules of the MC68VZ328 Table 1-2.
Modules of the MC68VZ328 and sleep. When in sleep mode, the CGM wakes up automatically when any unmasked external or internal interrupt occurs. See Chapter 4, “Clock Generation Module and Power Control Module,” for more detailed information. 1.3.3 System Control The primary function of the system control module is to provide configuration control of several other modules in the DragonBall VZ. These registers grant permission for access to many of the internal peripheral registers.
Modules of the MC68VZ328 1.3.8 General-Purpose I/O (GPIO) Lines The MC68VZ328 supports a maximum of 76 GPIO lines grouped together in ports A–G, J, K, and M. These ports can be configured as GPIO pins or dedicated peripheral interface pins. Each pin can be independently programmed as a GPIO pin even when other pins related to that on-chip peripheral are used as dedicated pins. For detailed information about programming these GPIO lines, see Chapter 10, “I/O Ports.” 1.3.
Modules of the MC68VZ328 1.3.13 Pulse-Width Modulators (PWM) The MC68VZ328 has two pulse-width modulators (PWMs). Each of the pulse-width modulators has three modes of operation—playback, tone, and digital-to-analog (D/A) conversion. Using these three modes, the PWM can be used to play back high-quality digital sounds, produce simple tones, or convert digital data into analog waveforms.
Modules of the MC68VZ328 1-12 MC68VZ328 User’s Manual
Chapter 2 Signal Descriptions This chapter describes the MC68VZ328’s input and output signals, which are organized into functional groups, as illustrated in Figure 2-1 on page 2-2. The MC68VZ328 uses a standard M68000 bus to communicate with on-chip and external peripherals. This single continuous bus exists both on and off the chip.
Signals Grouped by Function FLX68000 Static CPU Port A PA[7:0]/D[7:0] Memory Controller VDD LVDD VSS Port M Voltage Regulator D[15:8] A[19:17] PG0/BUSW/DTACK PG1/A0 LWE/LB UWE/UB OE PK[2:1]/UDS/LDS/RW 8/16-Bit 68000 Bus Interface Chip-Select 16-Bit Timer Port B MA[15:0/A[16:1] PM0/SDCLK PM1/SDCE PM2/DQMH PM3/DQML PM4/SDA10 PM5/DMOE CSA0 PF7/CSA1 PB0/CSB0 PB1/CSB1/SDWE PB2/CSC0/RAS0 PB3/CSC1/RAS1 PB4/CSD0/CAS0 PB5/CSD1/CAS1 PB6/TOUT/TIN PC[3:0]/LD[3:0] PC4/LFLM PC5/LLP PC6/LCLK PC7/LACD PF0/LC
Signals Grouped by Function Table 2-1.
Clock and System Control Signals 2.2 Power and Ground Signals The MC68VZ328 microprocessor has three types of power pins. They are VDD, VSS, and LVDD. • VDD—External power supply to drive all I/O pins and for the internal voltage regulator. It is recommended to place a 0.1 µF bypass capacitor close to each of these pins. • VSS—Signal return pin for both digital and analog circuits. • LVDD—Internal voltage regulator output signal that is used by the internal circuitry.
Data Bus Signals 1.2 s before its voltage is higher than 1.2 V to ensure that the crystal oscillator starts and stabilizes. See Section 4.3.1, “CLK32 Clock Signal,” on page 4-4 for details about selecting circuit values. This signal is inactive while the CPU is executing the RESET instruction. NOTE: When an R/C circuit is being used to generate the RESET signal to the MC68VZ328, the R/C circuit must be placed as close to the chip as possible. 2.
Interrupt Controller Signals 2.6 Bus Control Signals The bus control signals are used for both the configuration and operation of the MC68VZ328 bus. The following descriptions provide detailed information about programming the signals and their use. • LWE/LB, UWE/UB—Lower Byte Write-Enable and Upper Byte Write-Enable, or Lower Byte and Upper Byte data strobes. For all chip-select cycles except CSB[1:0], these two pins are LWE and UWE. They are used as lower and upper write-enable signals to a 16-bit port.
LCD Controller Signals • IRQ5/PF1—Interrupt Request 5 or Port F bit 1. This signal can be programmed as GPIO or as an interrupt input. When configured as an interrupt input, the signal may be programmed as a level high or level low trigger interrupt. This pin defaults to GPIO input pulled high. • EMIQ—Emulator Interrupt Status. This bit indicates that the in-circuit emulation module or EMUIRQ pin is requesting a level 7 interrupt.
Timer Signals • LCONTRAST/PF0—LCD Contrast and Port F bit 0. This output is generated by the pulse-width modulator (PWM) inside the LCD controller to adjust the supply voltage to the LCD panel. This pin can also be programmed as an I/O port. This pin defaults to GPIO input pulled high. 2.9 UART 1 and UART 2 Controller Signals There are two Universal Asynchronous Receive Transmit (UART) modules in the MC68VZ328. This section describes the signals that are used to interface with external serial devices.
Serial Peripheral Interface 2 Signals 2.11 Pulse-Width Modulator Signals There are two pulse-width modulator (PWM) modules in the MC68VZ328. This section describes the signals available to communicate with these PWM modules. • PWMO1/PB7—Pulse-Width Modulator Output 1 or Port B bit 7. PWMO1 is an output signal from the logical operation (AND or OR) of both the PWM 1 and PWM 2 modules. This pin defaults to GPIO input pulled high.
SDRAM Interface Signals 2.14 Chip-Select and EDO RAM Interface Signals Chip-select logic is used to provide maximum compatibility with a wide variety of memory logic. This section and Section 2.15, “SDRAM Interface Signals,” describe the signals used to interface with RAM, SDRAM, and EDO RAM. • CSA0—Chip-Select A bit 0. CSA0 is a default chip-select signal after reset.
In-Circuit Emulation (ICE) Signals 2.16 In-Circuit Emulation (ICE) Signals The ICE module is designed to support low-cost emulator designs using the MC68VZ328 microprocessor. There are four interface signals that are extended to external pins. • HIZ/P/D/PG3—High Impedance, Program/Data, or Port G bit 3. During system reset, a logic low of this input signal will put the MC68VZ328 into Hi-Z mode, in which all MC68VZ328 pins are three-stated after reset release.
In-Circuit Emulation (ICE) Signals 2-12 MC68VZ328 User’s Manual
Chapter 3 Memory Map The memory map is a guide to all on-chip resources. When you configure your chip, refer to Figure 3-1 and either Table 3-1 on page 3-2, which is sorted by address, or Table 3-2 on page 3-8, which is sorted alphabetically by register name.
Programmer’s Memory Map 3.1 Programmer’s Memory Map On reset the base address used in the table is 0xFFFFF000 (or 0xXXFFF000, where XX is “don’t care”). If a double-mapped bit is cleared in the system control register, then the base address is 0xFFFFF000 only. Unpredictable results occur if you write to any 4K register space not documented in Table 3-1 or Table 3-2 on page 3-8. Table 3-1.
Programmer’s Memory Map Table 3-1.
Programmer’s Memory Map Table 3-1.
Programmer’s Memory Map Table 3-1.
Programmer’s Memory Map Table 3-1.
Programmer’s Memory Map Table 3-1.
Programmer’s Memory Map Table 3-2.
Programmer’s Memory Map Table 3-2.
Programmer’s Memory Map Table 3-2.
Programmer’s Memory Map Table 3-2.
Programmer’s Memory Map Table 3-2.
Programmer’s Memory Map Table 3-2.
Programmer’s Memory Map 3-14 MC68VZ328 User’s Manual
Chapter 4 Clock Generation Module and Power Control Module This chapter describes the clock generation module (CGM) and power control module (PCM). The description of both modules comprises a single chapter because their operation is so closely integrated. The programmability of the individual clock signals makes the CGM a flexible clock source for the MC68VZ328 and its associated peripherals.
Introduction to the Clock Generation Module 4.1 Introduction to the Clock Generation Module The CGM produces four clock signals: • CLK32—A low-frequency reference clock used by almost every module • DMACLK—Used to create the remaining two clocks, and serves as DMA clock for the LCD controller • SYSCLK—Used by most modules, including the CPU • LCDCLK—Used as reference by the LCD The distribution of the clock signals generated by the CGM is shown in Table 4-1.
CGM Operational Overview 4.2 CGM Operational Overview The CGM consists of six major parts, as shown in the simplified block diagram in Figure 4-1. The clock source for the CGM is a crystal oscillator that is comprised of an external crystal connected to the internal XTAL oscillator circuit. The output of the XTAL oscillator is the CLK32 signal, whose frequency is determined by the frequency of the external crystal.
Detailed CGM Clock Descriptions 4.3 Detailed CGM Clock Descriptions Section 4.3.1, “CLK32 Clock Signal,” and Section 4.3.2, “PLLCLK Clock Signal,” describe in detail the operation of each clock signal produced by the CGM. 4.3.1 CLK32 Clock Signal The low-frequency output of the XTAL oscillator (CLK32) is available within a few hundred milliseconds after initial power is applied to the circuit. The frequency of the CLK32 signal is determined by the frequency of the external crystal.
Detailed CGM Clock Descriptions 4.3.2.1 PLLCLK Initial Power-up Sequence Refer to Figure 4-3 for a graphical representation of the following power-up sequence description. When power is initially applied to the MC68VZ328, the XTAL oscillator begins to oscillate. Due to the low-power design on the oscillator pads, the RESET signal must be asserted (low) for at least 1.2 s to ensure that the crystal oscillator starts and stabilizes.
Detailed CGM Clock Descriptions 4.3.2.2 PLL Frequency Selection Using the default settings for the PC and QC fields of the PLLFSR and a CLK32 input frequency of 32.768 kHz produces a PLLCLK output of 66.322 MHz. For a 38.400 kHz crystal, the same default settings produce a 77.722 MHz PLLCLK. The PLLCLK clock is phase locked to the CLK32 clock input signal. WARNING: The value of prescaler 1 must always be set to divide-by-two to prevent DMACLK and SYSCLK from operating beyond their design limits.
Detailed CGM Clock Descriptions Example 4-1. Configuring the PLLCLK Frequency NEWFREQ equ somevalue PLLCONTROL equ $FFFFF200 PLLFREQ equ $FFFFF202 TCOMPARE equ $FFFFF604 TCONTROL equ $FFFFF600 IMR equ $FFFFF304 ;P and Q value of new frequency ;PLL Control Register ;PLL Frequency Control Register ;Timer Compare Value Register ;Timer Control Register ;Interrupt Mask Register move.l IMR,-(SP) ;save the Interrupt Mask register move.l #$fffffffd,IMR ;enable ONLY Timer interrupt move.
CGM Programming Model 4.4 CGM Programming Model This section describes the two registers that enable and control the frequency of the CGM clocks. 4.4.1 PLL Control Register The PLL control register (PLLCR) controls the frequency selection of the LCDCLK, SYSCLK, and DMACLK. It also enables the output of the PLL and clock out/Port F pin 2 (CLKO/PF2). The settings for each bit and field in the register are described in Table 4-2.
CGM Programming Model Table 4-2. PLL Control Register Description (Continued) Name Description Setting DISPLL Bit 3 Disable PLL—This bit, when set, disables the output of the PLL, placing the chip in sleep mode, its lowest power state. 0 = PLL enabled (default). 1 = PLL disabled. Reserved Bit 2 Reserved This bit is reserved and should be set to 0. WKSEL Bits 1–0 Wake-up Clock Select—This field selects the delay of the PLL output from the initiation of the wake up until an output is available.
Introduction to the Power Control Module 4.4.2 PLL Frequency Select Register The PLL frequency select register (PLLFSR) controls the two dividers of the dual-modulus counter. It also contains the write-protect bit for the QC and PC counters and the CLK32 status bit. Although PLLFSR register can be accessed in bytes, it should always be written as a 16-bit word. The settings for each bit and field in the register is described in Table 4-4.
Introduction to the Power Control Module 4.5.1 Operating the PCM The power control module has four modes of operation: normal, burst, doze and sleep. In normal mode, the PCM is off. The MC68VZ328 enters burst mode when the PCM is enabled. In burst mode, the PCM controls the burst width of the CPUCLK signal to the CPU. If the burst width of the CPU clock is reduced to zero, CPUCLK is disabled and the MC68VZ328 is in doze mode. The lowest power mode setting is sleep mode.
Introduction to the Power Control Module 4.5.1.4 Sleep Mode Unlike burst or doze mode, sleep mode disables all of the clocks in the MC68VZ328 with the exception of the CLK32. The output of the PLL in the CGM is disabled in sleep mode through setting the DISPLL bit in the PLLCR register. Only the 32 kHz clock works to keep the real-time clock operational. Wake-up events activate the PLL, and the system clock starts operating after a delay determined by the WKSEL setting in the PLLCR.
Introduction to the Power Control Module CPU Bus Request CPU Bus Grant CPU Bus CPU Interface CLK32 Burst-Width Control SYSCLK Clock Control Width CPUCLK DMA Bus Grant PCTLR Wake-up DMA Bus Request Figure 4-4. Power Control Module Block Diagram If a wake-up event occurs while CPUCLK is disabled, the PCM is disabled and CPUCLK is immediately restored, allowing the CPU to process the event.
Introduction to the Power Control Module 4.5.4 Power Control Register The power control register (PCTLR) enables the power control module and determines when the CPUCLK signal is applied to the CPU. The settings for each bit and field in the register are described in Table 4-5. PCTLR Power Control Register BIT 7 6 5 0x(FF)FFF207 4 3 rw rw RESET rw 0 1 1 BIT 0 rw rw rw 1 1 1 WIDTH PCEN TYPE 2 0 0 1 0x1F Table 4-5.
Chapter 5 System Control This chapter describes the system control register of the MC68VZ328 microprocessor. The system control register enables system software to control and customize the following functions: • Access permission from the internal peripheral registers • Address space of the internal peripheral registers • Bus time-out control and status (bus error generator) 5.1 System Control Operation The on-chip resources use a reserved 4,096-byte block of address space for their registers.
Programming Model 5.2 Programming Model The following sections provide detailed programming information about the system control register and the other registers associated with its operation. 5.2.1 System Control Register The 8-bit read/write system control register (SCR) resides at the address 0xFFFFF000 or 0xXXFFF000 (where XX is “don’t care”) after reset. The SCR and all other internal registers cannot be accessed in the 68000’s user mode if the SO bit is set to 1.
Programming Model Table 5-1. System Control Register Description (Continued) Name Description Setting DMAP Bit 2 Double Map—This control bit controls the double-mapping function. 0 = The on-chip registers are mapped at 0xFFFFF000–0xFFFFFFFF. 1 = The on-chip registers are mapped at 0xFFFFF000–0xFFFFFFFF and 0xXXFFF000–0xXXFFFFF (XX = “don’t care”). Reserved Bit 1 Reserved This bit is reserved and reads 0.
Programming Model 5.2.2 Peripheral Control Register This register controls the PWM logical block operation, timer TIN/TOUT signal, and UART UCLK signal. The bit assignments for the register are shown in the following register display. The settings for the bits in the register are listed in Table 5-2. PCR Peripheral Control Register BIT 7 6 5 4 3 UCLK TYPE 0 0 0 0x(FF)FFF003 2 1 P[1:0] BIT 0 T[1:0] rw rw rw rw rw 0 0 0 0 0 RESET 0x00 Table 5-2.
Programming Model 5.2.3 ID Register This 32-bit read-only register shows the chip identification. The bit assignments for the register are shown in the following register display. The settings for the bits in the register are listed in Table 5-3.
Programming Model 5.2.4 I/O Drive Control Register This register controls the driving strength of all I/O signals. By default, all pins are defaulted to 4 mA driving current. After reset, system software should select 2 mA driving for those signals that do not need high-current driving for power saving. The bit assignments for the register are shown in the following display. The settings for the bits in the register are listed in Table 5-4.
Chapter 6 Chip-Select Logic This chapter describes the chip-select logic’s function and operation and provides programming information for controlling its operation. 6.1 Overview of the CSL The MC68VZ328 microprocessor contains eight general-purpose, programmable chip-select signals, which are used to select external devices on the address and data bus. The signals are arranged in four groups of two—CSA[1:0], CSB[1:0], CSC[1:0], and CSD[1:0].
Chip-Select Operation Table 6-1.
Chip-Select Operation chip-select–controlled area can be programmed as read/write, which provides optimal memory use, as shown in Figure 6-1. This area can be defined by programming the UPSIZ bits in the CSB, CSC, and CSD registers to between 32K and the entire chip-select area. Unprotected Memory (Read/Write) Up to 4 Mbyte Memory RAM CSB0 Up to 16 Mbyte Map CSB1 Up to 16 Mbyte Protected Memory (Supervisor-Only, Read-Only) Figure 6-1. Size Selection and Memory Protection for CSB0 and CSB1 6.2.
Programming Model 6.2.3 Overlapping Chip-Select Registers Do not program group address and chip-select registers to overlap, or the chip-select signals will overlap. Unused chip-selects must be disabled. Map them to an unused space, if possible. When the CPU tries to write to a read-only location that has already been programmed, the chip-select and DTACK signals will not be generated internally. BERR will be asserted internally if the bus error time-out function is enabled.
Programming Model CSGBB TYPE RESET Chip-Select Group B Base Address Register 0x(FF)FFF102 BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 GB B28 GB B27 GB B26 GB B25 GB B24 GB B23 GB B22 GB B21 GB B20 GB B19 GB B18 GB B17 GB B16 GB B15 GB B14 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIT 0 0 0x0000 Table 6-3.
Programming Model CSGBD TYPE RESET Chip-Select Group D Base Address Register 0x(FF)FFF106 BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 GB D2 8 GB D2 7 GB D2 6 GB D2 5 GB D2 4 GB D2 3 GB D2 2 GB D2 1 GB D2 0 GB D1 9 GB D1 8 GB D1 7 GB D1 6 GB D1 5 GB D1 4 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIT 0 0 0x0000 Table 6-5.
Programming Model Table 6-6. Chip-Select Upper Group Base Address Register Description (Continued) Name Description Setting Reserved Bit 11 Reserved This bit is reserved and should be set to 0. BGBA[31:29] Bits 10–8 MSB for Chip-Select B—The upper most significant bits for chip-select group B base address. The value will be ignored if UGEN is disabled. Enter value for bits 31–29 of chip-select register B. Reserved Bit 7 Reserved This bit is reserved and should be set to 0.
Programming Model 6.3.3 Chip-Select Registers There are four 16-bit chip-select (CSA, CSB, CSC, and CSD) registers for each corresponding chip-select base address register. Each register controls two chip-select signals and can be configured to select the memory type and size of the memory range supported as well as to program the required wait states or use the external DTACK signal. The settings for the registers are described in Table 6-7 through Table 6-10 on page 6-14.
Programming Model Table 6-7. Chip-Select Register A Description (Continued) Name SIZ Bits 3–1 Description Setting Chip-Select Size—This field determines the memory range of the chip-select. For CSAx and CSBx, the chip-select size is between 128K and 16 Mbyte. For CSCx and CSDx, the chip-select size is between 32K and 16 Mbyte. 000 = 128K (32K or 8 Mbyte* for CSCx and CSDx). 001 = 256K (64K or 16 Mbyte* for CSCx and CSDx). 010 = 512K (128K for CSCx and CSDx). 011 = 1 Mbyte (256K for CSCx and CSDx).
Programming Model CSB Chip-Select Register B BIT 15 14 13 RO SOP ROP rw rw rw 0 0 0 TYPE RESET 12 11 10 9 UPSIZ rw 0 0 0 0 0x(FF)FFF112 6 5 4 3 7 FLASH BSW rw rw rw rw rw rw rw rw w 0 0 0 0 0 0 0 0 0 WS3–1 2 1 BIT 0 8 SIZ EN 0x0000 Table 6-8. Chip-Select Register B Description Name Description Setting RO Bit 15 Read-Only—This bit sets the chip-select to read-only. Otherwise, read and write accesses are allowed.
Programming Model Table 6-8. Chip-Select Register B Description (Continued) Name WS3–1 Bits 6–4 Description Setting Wait State—This field determines the number of wait states added before an internal DTACK signal is returned for this chip-select. Note: When using the external DTACK signal, you must configure the BUSW/DTACK/PG0 pin. 000 = 0 + WS0 wait states. 001 = 2 + WS0 wait states. 010 = 4 + WS0 wait states. 011 = 6 + WS0 wait states. 100 = 8 + WS0 wait states. 101 = 10 + WS0 wait states.
Programming Model CSC TYPE RESET Chip-Select Register C BIT 15 14 13 RO SOP ROP rw rw rw 0 0 0 12 11 10 9 UPSIZ rw 0 0 0 0 0x(FF)FFF114 6 5 4 3 7 FLASH BSW rw rw rw rw rw rw rw rw w 0 0 0 0 0 0 0 0 0 WS3–1 2 1 BIT 0 8 SIZ EN 0x0000 Table 6-9. Chip-Select Register C Description Name Description Setting RO Bit 15 Read-Only—This bit sets the chip-select to read-only. Otherwise, read and write accesses are allowed.
Programming Model Table 6-9. Chip-Select Register C Description (Continued) Name WS3–1 Bits 6–4 Description Setting Wait State—This field determines the number of wait states added before an internal DTACK signal is returned for this chip-select. Note: When using the external DTACK signal, you must configure the BUSW/DTACK/PG0 pin. 000 = 0 + WS0 wait states. 001 = 2 + WS0 wait states. 010 = 4 + WS0 wait states. 011 = 6 + WS0 wait states. 100 = 8 + WS0 wait states. 101 = 10 + WS0 wait states.
Programming Model CSD TYPE RESET Chip-Select Register D BIT 15 14 13 RO SOP ROP rw rw rw 0 0 0 12 9 8 7 UPSIZ COMB DRAM FLASH BSW rw rw rw rw rw rw rw rw rw rw rw w 0 1 0 0 0 0 0 0 0 0 0 0 6 5 4 3 WS3–1 2 1 BIT 0 10 0 11 0x(FF)FFF116 SIZ EN 0x0200 Table 6-10. Chip-Select Register D Description Name Description Setting RO Bit 15 Read-Only—This bit sets the chip-select to read-only. Otherwise, read and write accesses are allowed.
Programming Model Table 6-10. Chip-Select Register D Description (Continued) Name FLASH Bit 8 Description Setting Flash Memory Support—When enabled, this bit provides support for flash memory by forcing the LWE/UWE signal to go active after chip-select. 0 = The chip-select and LWE/UWE signals go active at the same clock edge. 1 = The chip-select signal goes low 1 clock before LWE/UWE. Note: This bit is used for expanded memory size for CSD when the DRAM bit is enabled.
Programming Model 6.3.4 Emulation Chip-Select Register In addition to the eight general-purpose chip-select signals, the MC68VZ328 has an emulation chip-select register (EMUCS) that is specifically designed for the in-circuit emulation module. This register provides wait states 12–0, depending on the type of chip used. External logic (DTACK) may also be used to have longer wait states. EMUCS is only valid for the 0xFFFC0000–0xFFFDFFFF memory location.
Programming Model CSCTRL1 BIT 15 TYPE RESET 0 Chip-Select Control Register 1 14 13 12 11 10 9 8 EUP EN SR 16 EW S0 DW S0 CW S0 BW S0 AW S0 rw rw rw rw rw rw rw 0 0 0 0 0 0 0 7 6 0x(FF)FFF10A 5 DSI Z3 rw 0 0 4 3 DUP S2 rw 0 0 2 1 CUP S2 BIT 0 BUP S2 rw 0 0 rw 0 0 0x0000 Table 6-12. Chip-Select Control Register 1 Description Name Description Setting Reserved Bit 15 Reserved This bit is reserved and should be set to 0.
Programming Model Table 6-12. Chip-Select Control Register 1 Description (Continued) Name Description Setting Reserved Bit 3 Reserved This bit is reserved and should be set to 0. CUPS2 Bit 2 UPSIZ Bit 2 CSC Register—This is the most significant bit for UPSIZ[2:0] when the EUPEN bit is set. For information on calculating unprotected memory size, see Example 6-1. Reserved Bit 1 Reserved This bit is reserved and should be set to 0.
Programming Model Table 6-13. Chip-Select Control Register 2 Description (Continued) Name Description Setting ECDS Bit 14 Early Cycle Detection for Static Memory—This bit advances the chip-select signals for SRAM, ROM, or flash memory. It allows more setup time for slow memory without adding CPU wait states. 0 = Disabled. 1 = Enabled.
Programming Model 6.3.7 Chip-Select Control Register 3 This register controls minor timing trims for static memory access. CSCTRL3 TYPE RESET Chip-Select Control Register 3 BIT 15 14 13 12 11 10 EWE WPEXT LCWS AST DST CST rw rw rw rw rw rw 1 0 0 1 1 1 0x(FF)FFF150 9 8 7 6 5 4 3 2 1 BIT 0 0 0 0 0 0 0 0 0 0 0 0x9C00 Table 6-14.
Programming Model Example 6-2.
Programming Model 6-22 MC68VZ328 User’s Manual
Chapter 7 DRAM Controller This chapter describes the DRAM controller for the MC68VZ328. The operation of the DRAM controller is closely linked to the chip-select logic. Please refer to Chapter 6, “Chip-Select Logic,” for more details. 7.1 Introduction to the DRAM Controller The DRAM controller provides a glueless interface for either 8-bit or 16-bit DRAM. It supports EDO RAM, Fast Page Mode, and synchronous DRAM.
Introduction to the DRAM Controller Mode Control Address Data Control CSD0 MPU Interface CLK32 SYSCLK Refresh Control RAS0 DRAM Signal Control RAS1 CAS0 CAS1 CSD1 Page Access (from LCD) 8-Bit Port (from SIM) A[31:1] DTACK Control DRAM Address Control MD[15:0] Figure 7-1.
DRAM Controller Operation 7.2 DRAM Controller Operation This section describes the DRAM controller’s operation. 7.2.1 Address Multiplexing The address multiplexer can support a wide variety of memory devices in either 8- or 16-bit mode. The upper internal address lines from the CPU or LCD controller provide the row address, and the lower internal address lines are used as the column address. This scheme enables the use of Fast Page Mode or EDO RAM mode read accesses to the DRAM during LCD DMA cycles.
DRAM Controller Operation Table 7-1.
DRAM Controller Operation Table 7-2 through Table 7-5 on page 7-6 provide recommendations for MC68VZ328–to–SDRAM connections and for selecting multiplexing options for different types of SDRAM. Table 7-2.
DRAM Controller Operation Table 7-4.
DRAM Controller Operation 7.2.2 DTACK Generation In a 16 MHz system frequency, 60 ns DRAM can support a zero wait state (4 clocks per access) for CPU bus cycles. Therefore, DTACK is only delayed for refresh operations that occur before a read/write access cycle. The value of N clocks (N is the number of system clock cycles required for refresh) will be inserted into a read or write cycle when the CPU cycle collides with a refresh cycle. Refresh, in this case, has a higher priority.
DRAM Controller Operation 7.2.4 LCD Interface Figure 7-2 illustrates the LCD controller and DRAM controller interface. The DRAM controller supports page bursting accesses. When the PAGE_ACCESS signal is active and CSD[1:0] is active, Fast Page Mode or EDO RAM mode will be initiated. In Fast Page Mode mode, the first access will always be 4 clocks. Additional clocks may be added to the access cycle for the second and subsequent access cycles using the BC0 and BC1 bits of the DRAMC register.
DRAM Controller Operation 7.2.5 8-Bit Mode From the system integration module (SIM), 8-bit operation on the fly can be selected using the signal 8-bit port. If one of the CSDx signals is programmed as 8-bit mode, the 8-bit mode signal will be active at the same time that CSDx is active.
DRAM Controller Operation 7.2.7 Data Retention During Reset DRAM needs to retain data during reset, whether it is an external reset or an internal watchdog reset. The DRAM controller itself has a special design to support this feature. Figure 7-3 illustrates the timing for data retention. 32 kHz External RESET (Hardware reset) Internal RESET DRAM Refresh 15.6 µs CPCRESET DRAM Reset Port (CSCx, CSDx) Reset DRAM Sync.
DRAM Controller Operation 7.2.8 Data Retention Sequence Data is retained in the following sequence: 1. The external RESET signal is sent to the MC68VZ328. 2. The internal RESET signal is generated by synchronizing the external RESET signal with the CLK32 signal. 3. When the internal RESET is asserted, the DRAM controller will stop the current refresh operation and enter burst refresh mode, which is a consecutive CAS-before-RAS refresh cycle. 4. The external RESET signal continues asserting. 5.
Programming Model 7.3 Programming Model This section describes the programming model for the DRAM controller. 7.3.1 DRAM Memory Configuration Register The DRAM memory configuration register (DRAMMC) is used to set the DRAM refresh interval and configure the address multiplexer for the specific memory device being used. The bit position and values are shown in the following register display. The details about the register settings are described in Table 7-6.
Programming Model Table 7-6. DRAM Memory Configuration Register Description (Continued) Name REF Bits 4–0 Description Refresh Cycle—This value determines the refresh rate for the DRAM controller. The refresh rate can be calculated using the equation shown in Example 7-1. Setting See description The REF value is the time of 1 refresh cycle. Example 7-1. Calculating REF Field Values for Refresh Times When CLK = 0, 32 kHz (or 34.8 kHz) is used for refresh control.
Programming Model 7.3.2 DRAM Control Register The DRAM control (DRAMC) register is used to control the operation of the DRAM controller. The bit position and values are shown in the following register display. The details about the register settings are described in Table 7-7.
Programming Model Table 7-7. DRAM Control Register Description (Continued) Name Description Setting LSP Bit 4 Light Sleep—Setting this bit enables the core or LCD controller to access the DRAM when the RM bit is set (DRAM is in self-refresh mode). Self-refresh mode is temporarily interrupted for the DRAM access and automatically returns to self-refresh mode once the transfer is complete. Transfers in this mode are much slower than normal.
Programming Model 7.3.3 SDRAM Control Register This register controls operation when SDRAM is being used. The bit position and values are shown in the following register display. The details about the register settings are described in Table 7-8.
Programming Model Table 7-8. SDRAM Control Register Description (Continued) Name Description BNKADDL Bits 3–2 Setting SDRAM Low Order Bank Address Line Selection—A 2-bit bank register selection address is generated by selecting the appropriate CPU address line. This register bit allows selection of the low order bit. 00 = PA19. 01 = PA21. 10 = PA23. 11 = Force this bank address line to 0. See Table 7-9 for programming examples.
Programming Model 7.3.4 SDRAM Power-down Register This register controls how the SDRAM and the MC68VZ328 operate during a power-down operation. The bit position and values are shown in the following register display. The details about the register settings are described in Table 7-10.
Chapter 8 LCD Controller This chapter describes the operation of the liquid crystal display (LCD) controller and supplies the programming information necessary to implement it in design projects. The LCD controller provides display data for external LCD drivers or for an LCD panel. The LCD controller fetches display data directly from system memory through periodic DMA transfer cycles. For this reason, an understanding of the DRAM controller is recommended.
LCD Controller Operation Address Data Bus Bus DMACLK CPU Interface Registers Pixel Clock LCD Controller LCD Interface CPU BR Control Logic Frame Rate Control BG Screen DMA SIM CSxx LCD Driver Cursor Logic OE Line Buffer System Memory PWM LCD Bias Voltage Control Figure 8-1. LCD Controller Block Diagram 8.
LCD Controller Operation The LCD interface logic is used to pack the display data into the correct size and output it to the LCD panel’s data bus. The polarity of the LFLM, LP, and LCLK signals and pixel data can all be programmed to suit different LCD panel requirements. 8.2.1 Connecting the LCD Controller to an LCD Panel The following signals are used to connect the LCD controller to an LCD panel: • LD[7:0]—The LCD Data bus lines transfer pixel data to the LCD panel so that it can be displayed.
LCD Controller Operation LFLM LLP LINE 1 LINE 2 LINE 3 LINE 4 LINE n LINE 1 LLP 1 2 3 20 21 m-1 m LCLK 4-bit LCD data bus (PBSIZ = 10) LD3 [0,0] [4,0] [8,0] [76,0] [80,0] [m-8,0] [m-4,0] LD2 [1,0] [5,0] [9,0] [77,0] [81,0] [m-7,0] [m-3,0] LD1 [2,0] [6,0] [10,0] [78,0] [82,0] [m-6,0] [m-2,0] LD0 [3,0] [7,0] [11,0] [79,0] [83,0] [m-5,0] [m-1,0] 2-bit LCD data bus (PBSIZ = 01) LD1 [0,0] [2,0] [4,0] [38,0] [40,0] [m-4,0] [m-2,0] LD0 [1,0] [3,0] [5,0] [3
LCD Controller Operation Virtual Page Width Screen Starting Address Cursor X Position Cursor Height Cursor Y Position Screen Height Virtual Page Height Screen Width Cursor Width Figure 8-3. LCD Screen Format The LCD screen width (LXMAX) and LCD screen height (LYMAX) registers are where the size of the LCD panel is specified. The LCD controller will start scanning the display memory at the location pointed to by the LCD screen starting address (LSSA) register.
LCD Controller Operation 8.2.2.3 Mapping the Display Data The LCD controller supports 1 or 2 bits per pixel graphics mode. In the 1-bit mode, each bit in the display memory corresponds to a pixel in the LCD panel. The corresponding pixel on the screen is either fully on or fully off. In 2-bit mode, each pixel is represented by two bits of display memory. To map the data to the LCD panel, program the appropriate bit in the corresponding address of the display memory.
LCD Controller Operation Table 8-1. Grey Palette Density Gray Code (Hex) Density Density (in Decimal) 0 0 0 1 1/8 0.125 2 1/5 0.2 3 1/4 0.25 4 1/3 0.333 5 2/5 0.4 6 4/9 0.444 7 1/2 0.5 8 5/9 0.555 9 3/5 0.6 A 2/3 0.666 B 3/4 0.75 C 4/5 0.8 D 7/8 0.875 E 14/15 0.933 F 1 1 Since crystal formulations and driving voltages vary, the visual grayscale effect may or may not be linearly related to the frame rate.
LCD Controller Operation 8.2.3 Using Low-Power Mode Some panels may have a PANEL_OFF signal, which is used to turn off the panel for low-power mode. In an MC68VZ328 system, this signal is not supported, but can be easily implemented using a parallel I/O pin. The software can be programmed to achieve PANEL_OFF by using parallel I/O in the following sequence: 1. Drive the LCD bias voltage to 0 V. 2. Set the LCDON bit to 0 in the LCD clocking control (LCKCON) register, turning off the LCD controller.
LCD Controller Operation 1 1 T l = --------------- × ---------------------60 Hz 240 lines = 69.4 µs During the same period, the line buffer must be filled. The following TDMA duration is how long the DMA cycle will hold up the bus: pixels × 2 bits per pixel × 2 clocksTDMA = 320 ---------------------------------------------------------------------------------------------------16.67 MHz × 16-bit bus = 4.8 µs Thus, the percentage of host bus time taken up by the LCD controller’s DMA is PDMA: 4.
Programming Model 8.3 Programming Model The remaining sections of this chapter provide detailed descriptions of the registers, their settings, and sample programming examples. 8.3.1 LCD Screen Starting Address Register The LCD screen starting address (LSSA) register is used to inform the LCD panel where to fetch the data to be displayed. The bit assignments for the register are shown in the following register display. The settings for the bits in the register are listed in Table 8-2.
Programming Model 8.3.2 LCD Virtual Page Width Register The LCD virtual page width (LVPW) register contains the width of the displayed image. The bit assignments for the register are shown in the following register display. The settings for the bits in the register are listed in Table 8-3. LVPW LCD Virtual Page Width Register 0x(FF)FFFA05 BIT 7 6 5 4 3 2 1 BIT 0 VP8 VP7 VP6 VP5 VP4 VP3 VP2 VP1 rw rw rw rw rw rw rw rw 1 1 1 1 1 1 1 1 TYPE RESET 0xFF Table 8-3.
Programming Model 8.3.4 LCD Screen Height Register The LCD screen height register (LYMAX) is used to define the height of the LCD panel’s screen in pixels. The bit assignments for the register are shown in the following register display. The settings for the bits in the register are listed in Table 8-5.
Programming Model Table 8-6. LCD Cursor X Position Register Description (Continued) Name Description CXPx Bits 9–0 Setting Cursor X Position 9–0—These bits represent the cursor’s horizontal starting position, X, in terms of pixel count (from 0 to XMAX). See description. 8.3.6 LCD Cursor Y Position Register The LCD cursor Y position (LCYP) register is used to determine the vertical pixel position of the cursor on the LCD panel.
Programming Model 8.3.7 LCD Cursor Width and Height Register The LCD cursor width and height (LCWCH) register is used to determine the width and height of the cursor, in screen pixels. The bit assignments for the register are shown in the following register display. The settings for the bits in the register are listed in Table 8-8.
Programming Model LBLKC LCD Blink Control Register TYPE 0x(FF)FFFA1F BIT 7 6 5 4 3 2 1 BIT 0 BKEN BD6 BD5 BD4 BD3 BD2 BD1 BD0 rw rw rw rw rw rw rw rw 0 1 1 1 1 1 1 1 RESET 0x7F Table 8-9. LCD Blink Control Register Description Name Description Setting BKEN Bit 7 Blink Enable—This bit determines if the cursor will blink or remain steady.
Programming Model 8.3.10 LCD Polarity Configuration Register The LCD polarity configuration (LPOLCF) register controls the polarity of the interface signal that goes to the LCD panel. The bit assignments for the register are shown in the following register display. The settings for the bits in the register are listed in Table 8-11.
Programming Model LACDRC LACD Rate Control Register 0x(FF)FFFA23 BIT 7 6 5 4 3 2 1 BIT 0 ACDSLT ACD6 ACD5 ACD4 ACD3 ACD2 ACD1 ACD0 rw rw rw rw rw rw rw rw 0 0 0 0 0 0 0 0 TYPE RESET 0x00 Table 8-12. LACD Rate Control Register Description Name Description Setting ACDSLT Bit 7 Clock Source Select—This bit selects the clock source for the internal counter that generates an LACD signal.
Programming Model 8.3.13 LCD Clocking Control Register The LCD clocking control (LCKCON) register is used to enable the LCD controller and control the LCD memory cycle. The bit assignments for the register are shown in the following register display. The settings for the bits in the register are listed in Table 8-14. LCKCON LCD Clocking Control Register BIT 7 6 5 4 rw rw rw rw 0 0 0 0 3 LCDON TYPE RESET 0x(FF)FFFA27 2 1 BIT 0 rw rw rw rw 0 0 0 0 Unused 0x00 Table 8-14.
Programming Model Table 8-15.
Programming Model 8.3.17 LCD Gray Palette Mapping Register For four-level grayscale displays, full black and full white are the two predefined display levels. The other two intermediate grayscale shading densities can be adjusted in the LCD gray palette mapping register (LGPMR). The bit assignments for the register are shown in the following register display. The settings for the bits in the register are listed in Table 8-17.
Programming Model Table 8-18. PWM Contrast Control Register Description (Continued) Name Description Setting CCPEN Bit 8 Contrast Control Enable—This bit is used to enable or disable the contrast control function. 0 = Contrast control is off. 1 = Contrast control is on. PWx Bits 7–0 Pulse Width 7–0—This bit controls the pulse-width of the built-in pulse-width modulator, which controls the contrast of the LCD screen. See Chapter 15, “Pulse-Width Modulator 1 and 2,” for more information.
Programming Example 8.3.20 DMA Control Register The LCD controller contains an 8 × 16 pixel buffer, which stores DMA-in data from system memory. This data is then passed to the LCD for display. When enough data has been removed from the buffer that it needs to be refilled, a new DMA transfer must be initiated. The DMA control register controls when the buffer should be refilled and the DMA burst length used when refilling. The bit assignments for the register are shown in the following register display.
Chapter 9 Interrupt Controller This chapter describes the interrupt controller and all of the signals associated with it. The interrupt controller of the MC68VZ328 supports all internal interrupts as well as external edge- and level-sensitive interrupts. There are seven interrupt levels. Level 7 has the highest priority and level 1 has the lowest.
Interrupt Processing 9.1 Interrupt Processing Interrupts on the MC68VZ328 are processed as illustrated in the flowchart shown in Figure 9-1. Details on each stage of the flow diagram are as follows: 1. The interrupt controller collects interrupt events from both on- and off-chip peripherals. Next, it prioritizes them and presents the highest priority request to the CPU if there are no higher interrupts pending; otherwise, the highest priority interrupt is served first. 2.
Exception Vectors programmable, but the lower 3 bits reflect the interrupt level that is being serviced. All interrupts are maskable. Writing a 1 to a bit in the interrupt mask register disables that interrupt. If an interrupt is masked, you can find out its status in the interrupt pending register. 9.2 Exception Vectors A vector number is an 8-bit number that can be multiplied by four to obtain the address of an exception vector.
Reset Table 9-1.
Interrupt Controller Operation NOTE: The MC68VZ328 supports the reset instruction. However, it only resets the CPU, and the RESET pin will not go low when this instruction is issued because it is an input-only signal. The MC68VZ328’s RESET signal should be held low for at least 1.2 s after VDD is applied. See Section 4.3.2.1, “PLLCLK Initial Power-up Sequence,” on page 4-5 for detailed information about selecting the optimum RESET delay.
Vector Generation 9.4.2 Interrupt Vectors The MC68VZ328 provides one interrupt vector for each of the seven user interrupt levels. These interrupt vectors form the user interrupt vector section of Table 9-1 on page 9-3. The user interrupt vectors can be located anywhere within the 0x100 to 0x400 address range. The 5 most significant bits of the interrupt vector number are programmable, but the lower 3 bits reflect the interrupt level being serviced. All interrupts are maskable by the interrupt controller.
Programming Model 9.6 Programming Model This section describes registers that you may need to configure so that the interrupt controller can properly process interrupts, generate vector numbers, and post interrupts to the core. NOTE: When programmed as edge-triggered interrupts, all external interrupts (INT[3:0], IRQ1, IRQ2, IRQ3, and IRQ6) can be cleared by writing a 1 to the corresponding status bit in the interrupt status register (ISR).
Programming Model 9.6.2 Interrupt Control Register The interrupt control register (ICR) controls the behavior of the external interrupt inputs. It informs the interrupt controller whether the interrupt signal is an edge-triggered or a level-sensitive interrupt, as well as whether it has positive or negative polarity. The bit assignments for this register are shown in the following register display, and the settings for the bit positions are listed in Table 9-4.
Programming Model Table 9-4. Interrupt Control Register Description (Continued) Name Description Setting ET2 Bit 10 IRQ2 Edge Trigger Select—When this bit is set, the IRQ2 signal is an edge-triggered interrupt. In edge-triggered mode, a 1 must be written to the IRQ2 bit in the interrupt status register to clear this interrupt. When this bit is low, IRQ2 is a level-sensitive interrupt. In this case, the external source of the interrupt must be cleared. 0 = Level-sensitive interrupt.
Programming Model 9.6.3 Interrupt Mask Register The interrupt mask register (IMR) can mask out a particular interrupt if the corresponding bit for the interrupt is set. There is one control bit for each interrupt source. When an interrupt is masked, the interrupt controller will not generate an interrupt request to the CPU, but its status can still be observed in the interrupt pending register. At reset, all the interrupts are masked and all the bits in this register are set to 1.
Programming Model Table 9-5. Interrupt Mask Register Description (Continued) Name Description Settings MIRQ2 Bit 17 Mask IRQ2 Interrupt—When set, this bit indicates that IRQ2 is masked. It is set to 1 after reset. 0 = Enable IRQ2 interrupt. 1 = Mask IRQ2 interrupt. MIRQ1 Bit 16 Mask IRQ1 Interrupt—When set, this bit indicates that IRQ1 is masked. It is set to 1 after reset. 0 = Enable IRQ1 interrupt. 1 = Mask IRQ1 interrupt.
Programming Model 9.6.4 Interrupt Status Register During the interrupt service, the interrupt handler determines the source of interrupts by examining the interrupt status register (ISR). When the bits in this register are set, they indicate that the corresponding interrupt is posted to the core. If there are multiple interrupt sources at the same level, the software handler may need to prioritize them, depending on the application.
Programming Model Table 9-6. Interrupt Status Register Description (Continued) Name Description Settings RTI Bit 22 Real-Time Interrupt Status (Real-Time Clock)—When set, this bit indicates that the real-time timer has reached its predefined frequency count. The frequency can be selected inside the real-time clock module, which can function as an additional timer. 0 = Real-time timer has not reached predefined frequency count. 1 = Real-time timer has reached predefined frequency count.
Programming Model Table 9-6. Interrupt Status Register Description (Continued) Name Description Settings UART2 Bit 12 UART 2 Interrupt Request—When set, this bit indicates that the UART 2 module needs service. The interrupt level is configurable from level 1 to level 6. See Section 9.6.6, “Interrupt Level Register,” for more details. 0 = No UART 2 interrupt request is pending. 1 = UART 2 interrupt request is pending.
Programming Model Table 9-6. Interrupt Status Register Description (Continued) Name Description Settings UART1 Bit 2 UART 1 Interrupt Request—When set, this bit indicates that the UART 1 module needs service. This is a level 4 interrupt. 0 = No UART1 service request is pending. 1 = UART1 service is needed. TMR1 Bit 1 Timer 1 Interrupt Status—This bit indicates that a timer 1 event has occurred. This is a level 6 interrupt. 0 = No timer 1 event occurred. 1 = A timer 1 event has occurred.
Programming Model 9.6.5 Interrupt Pending Register The read-only interrupt pending register (IPR) indicates which interrupts are pending. If an interrupt source requests an interrupt, but that interrupt is masked by the interrupt mask register, then that interrupt bit will be set in this register, but not in the interrupt status register. If the pending interrupt is not masked, the interrupt bit will be set in both registers.
Programming Model Table 9-7. Interrupt Pending Register Description (Continued) Name Description Settings IRQ5 Bit 20 Interrupt Request Level 5—This bit, when set, indicates that an external device is requesting an interrupt on level 5. If the IRQ5 signal is set to be a level-sensitive interrupt, the source of the interrupt must first be cleared. 0 = No level 5 interrupt is pending. 1 = A level 5 interrupt is pending.
Programming Model Table 9-7. Interrupt Pending Register Description (Continued) Name Description Settings INT2 Bit 10 External INT2 Interrupt—This bit, when set, indicates that a level 4 interrupt has occurred. It is usually for a keyboard interface. When it is programmed as edge-triggered, it can only be cleared by writing a 1 to the port D register. See Section 10.4.5, “Port D Registers,” on page 10-16 for details. 0 = No INT2 interrupt is pending. 1 = An INT2 interrupt is pending.
Programming Model 9.6.6 Interrupt Level Register TIMER 2, UART 2, PWM 2, and SPI 1 are new modules to the MC68VZ328 compared to the previous version, MC68EZ328. Interrupts generated from these modules are level configurable. The interrupt level control register (ILCR) controls the interrupt level for these interrupts.
Pen Interrupts 9.7 Keyboard Interrupts Keyboard interrupt features provide a smart power-management capability. The CPU core can be put to sleep when no key is being pressed. Once a key is pressed, however, the core wakes up to service the request. This event-driven approach significantly reduces power consumption. KB0 to KB7 (multiplexed with INT[3:0], IRQ1, IRQ2, IRQ3, and IRQ6) are input pins for the keyboard interface.
Chapter 10 I/O Ports This chapter describes the 10 multipurpose ports of the MC68VZ328. It also describes how to use the ports for external I/O control and to determine the status of the external signals. All 10 ports (A–G, J, K, and M) are programmable I/O ports with pull-up and pull-down capability. Each port can be used as a general-purpose I/O (GPIO) port, or it can be connected to its dedicated I/O function. Every signal line connects to an external pin.
Status of I/O Ports During Reset Table 10-1.
Status of I/O Ports During Reset System Clock (SYSCLK) 32 kHz Clock External Reset (Hardware Reset) External Reset Time Length Internal Reset 16 SYSCLK Cycles Internal Reset Pulse Ports A, C, D, E, F, G, J, & K Default State Reset Assertion Time Length Default State Ports B & M Figure 10-1. I/O Port Warm Reset Timing As shown in Figure 10-1, resets for Ports A, C–G, J, and K are triggered by the assertion of the internal reset signal.
I/O Port Operation 10.2.3 Summary of Port Behavior During Reset Table 10-2 summarizes the behavior of all MC68VZ328 I/O ports during the Reset Assertion Time Length (see Figure 10-1 on page 10-3) for power-up resets and warm resets. Table 10-2.
I/O Port Operation Data to Module Signal Pull-up Enable Register Data from Module Signal Pad Buffer 0 Pad Data Register 1 SEL Output Enable from Module Signal 0 Direction Register 1 SEL Select Register Figure 10-2. I/O Port Operation For example, if Figure 10-2 represents the D0 bit of Port E, when the SEL0 in the select register is cleared, the “data from module” line is connected to the serial peripheral interface module’s TXD signal (SPITXD).
Programming Model 10.3.4 Port Pull-up and Pull-down Resistors The pull-up and pull-down resistors are enabled by setting the pull-up or pull-down enable register’s bits to 1. Pull-up and pull-down resistors can be selected individually regardless of whether the I/O port is selected or not. After reset, Ports A–F, J, K, and M default to the I/O function with internal pull-up or pull-down enabled. Resistor assignments for individual ports is shown in Table 10-3.
Programming Model 10.4.1.1 Port A Direction Register The Port A direction register controls the direction (input or output) of the line associated with the PADATA bit position. The settings for the bit positions are shown in Table 10-4. PADIR Port A Direction Register TYPE RESET 0x(FF)FFF400 BIT 7 6 5 4 3 2 1 BIT 0 DIR7 DIR6 DIR5 DIR4 DIR3 DIR2 DIR1 DIR0 rw rw rw rw rw rw rw rw 0 0 0 0 0 0 0 0 0x00 Table 10-4.
Programming Model 10.4.1.3 Port A Pull-up Enable Register The Port A pull-up enable register (PAPUEN) controls the pull-up resistors for each line in Port A. The settings for the bit positions are shown in Table 10-6. PAPUEN TYPE RESET Port A Pull-up Enable Register 0x(FF)FFF402 BIT 7 6 5 4 3 2 1 BIT 0 PU7 PU6 PU5 PU4 PU3 PU2 PU1 PU0 rw rw rw rw rw rw rw rw 1 1 1 1 1 1 1 1 0xFF Table 10-6.
Programming Model PBDIR TYPE RESET Port B Direction Register 0x(FF)FFF408 BIT 7 6 5 4 3 2 1 BIT 0 DIR7 DIR6 DIR5 DIR4 DIR3 DIR2 DIR1 DIR0 rw rw rw rw rw rw rw rw 0 0 0 0 0 0 0 0 0x00 Table 10-7. Port B Direction Register Description Name DIRx Bits 7–0 Description Setting Direction—These bits control the direction of the pins. They reset to 0. With the exception of bit 6, if a bit is selected as a dedicated I/O in PBSEL, the DIR bit is ignored.
Programming Model 10.4.2.3 Port B Dedicated I/O Functions The eight PBDATA lines are multiplexed with the chip-select, DRAM control, TIN/TOUT, and PWM dedicated I/O signals whose assignments are shown in Table 10-9. Table 10-9.
Programming Model PBPUEN Port B Pull-up Enable Register TYPE RESET 0x(FF)FFF40A BIT 7 6 5 4 3 2 1 BIT 0 PU7 PU6 PU5 PU4 PU3 PU2 PU1 PU0 rw rw rw rw rw rw rw rw 1 1 1 1 1 1 1 1 0xFF Table 10-10. Port B Pull-up Enable Register Description Name Description PUx Bits 7–0 Setting Pull-up—These bits enable the pull-up resistors on the port. 0 = Pull-up resistors are disabled 1 = Pull-up resistors are enabled 10.4.2.
Programming Model 10.4.3.1 Port C Direction Register The Port C direction register controls the direction (input or output) of the line associated with the PCDATA bit position. When the data bit is assigned to a dedicated I/O function by the PCSEL register, the DIR bits are ignored. The settings for the bit positions are shown in Table 10-12.
Programming Model accept the data, but the data written to each cannot be accessed until the corresponding pin is configured as an output. The actual value on the pin is reported when these bits are read, regardless of whether they are configured as input or output. 10.4.3.3 Port C Dedicated I/O Functions The eight PCDATA lines are multiplexed with the LCD controller dedicated I/O signals whose assignments are shown in Table 10-14. Table 10-14.
Programming Model 10.4.3.5 Port C Select Register The Port C select register (PCSEL) determines if a bit position in the Port C data register (PCDATA) is assigned as a GPIO or to a dedicated I/O function. The settings for the bit positions are shown in Table 10-16. PCSEL TYPE RESET Port C Select Register 0x(FF)FFF413 BIT 7 6 5 4 3 2 1 BIT 0 SEL7 SEL6 SEL5 SEL4 SEL3 SEL2 SEL1 SEL0 rw rw rw rw rw rw rw rw 1 1 1 1 1 1 1 1 0xFF Table 10-16.
Programming Model 10.4.4 Port D Operation Port D has the same functionality as other GPIO ports, except that it also has interrupt capabilities. It should be used as either a general-purpose, interrupt-generating port or as a keyboard input port. Figure 10-3 illustrates how this type of port operates.
Programming Model 10.4.5 Port D Registers Unlike the other ports, Port D is unique in that it is comprised of eight 8-bit I/O registers.
Programming Model 10.4.5.2 Port D Data Register The settings for the PDDATA bit positions are shown in Table 10-18. PDDATA Port D Data Register TYPE 0x(FF)FFF419 BIT 7 6 5 4 3 2 1 BIT 0 D7 D6 D5 D4 D3 D2 D1 D0 rw rw rw rw rw rw rw rw 1 1 1 1 1 1 1 1 RESET 0xFF* *Actual bit value depends on external circuits connected to pin. Table 10-18. Port D Data Register Description Name Dx Bits 7–0 Description Data—These bits reflect the status of the I/O signal.
Programming Model 10.4.5.3 Port D Interrupt Options Interrupt bits 3–0 (INT[3:0]), interrupt request bits 3–1 (IRQ[3:1]), interrupt request bit 6 (IRQ6), or Port D bits 7–0 can be configured as edge- or level-triggered interrupt signals. NOTE: When external interrupts INT[3:0], IRQ1, IRQ2, IRQ3, and IRQ6 are programmed as edge-triggered interrupts, they can be cleared by writing a 1 to the corresponding status bit in the interrupt status register in the interrupt controller.
Programming Model 10.4.5.5 Port D Select Register The Port D select register (PDSEL) determines if a bit position in the Port D data register (PDDATA) is assigned as a GPIO or to a dedicated I/O function. The settings for the bit positions of PDSEL are shown in Table 10-21. PDSEL Port D Select Register TYPE RESET BIT 7 6 5 4 SEL7 SEL6 SEL5 SEL4 rw rw rw rw 1 1 1 1 0x(FF)FFF41B 3 2 1 BIT 0 0 0 0 0 0xF0 Table 10-21.
Programming Model 10.4.5.7 Port D Interrupt Request Enable Register The interrupt enable bits (IQEN[3:0]) determine which INT[3:0] will generate an interrupt to the interrupt controller module. The settings for the bit positions of PDIRQEN are shown in Table 10-23. PDIRQEN Port D Interrupt Request Enable Register BIT 7 6 5 4 3 2 1 BIT 0 IQEN3 IQEN2 IQEN1 IQEN0 rw rw rw rw 0 0 0 0 TYPE RESET 0 0 0 0x(FF)FFF41D 0 0x00 Table 10-23.
Programming Model PDIRQEG Port D Interrupt Request Edge Register BIT 7 6 5 4 TYPE 0 RESET 0 0 0 0x(FF)FFF41F 3 2 1 BIT 0 IQEG3 IQEG2 IQEG1 IQEG0 rw rw rw rw 0 0 0 0 0x00 Table 10-25. Port D Interrupt Request Edge Register Description Name Description Setting Reserved Bits 7–4 Reserved These bits are reserved and should be set to 0. IQEGx Bits 3–0 Edge Enable—The polarity of the rising or falling edge is selected by the POLx bits.
Programming Model 10.4.6.2 Port E Data Register The settings for the bit positions of the PEDATA register are shown in Table 10-27. PEDATA TYPE Port E Data Register 0x(FF)FFF421 BIT 7 6 5 4 3 2 1 BIT 0 D7 D6 D5 D4 D3 D2 D1 D0 rw rw rw rw rw rw rw rw 1 1 1 1 1 1 1 1 RESET 0xFF* *Actual bit value depends on external circuits connected to pin. Table 10-27.
Programming Model Table 10-28. Port E Dedicated Function Assignments (Continued) Bit GPIO Function Dedicated I/O Function 6 Data bit 6 RTS1 7 Data bit 7 CTS1 10.4.6.4 Port E Pull-up Enable Register The Port E pull-up enable register (PEPUEN) controls the pull-up resistors for each line in Port E. The settings for the bit positions of the PEPUEN register are shown in Table 10-29.
Programming Model 10.4.7 Port F Registers Port F is composed of the following 8-bit general-purpose I/O registers: • Port F direction register (PFDIR) • Port F data register (PFDATA) • Port F pull-up enable register (PFPUEN) • Port F select register (PFSEL) Each signal in the PFDATA register connects to an external pin. As on the other ports, each bit on Port F is individually configured. 10.4.7.
Programming Model 10.4.7.2 Port F Data Register The settings for the bit positions of the PFDATA register are shown in Table 10-32. PFDATA Port F Data Register TYPE 0x(FF)FFF429 BIT 7 6 5 4 3 2 1 BIT 0 D7 D6 D5 D4 D3 D2 D1 D0 rw rw rw rw rw rw rw rw 1 1 1 1 1 1 1 1 RESET 0xFF* *Actual bit value depends on external circuits connected to pin. Table 10-32.
Programming Model 10.4.7.3 Port F Dedicated I/O Functions The eight PFDATA lines are multiplexed with the dedicated I/O signals whose assignments are shown in Table 10-33. Table 10-33.
Programming Model 10.4.7.4 Port F Pull-up/Pull-down Enable Register The Port F pull-up/pull-down enable register (PFPUEN) controls the pull-up resistors for each line in Port F. The settings for the PFPUEN bit positions are shown in Table 10-34. PFPUEN Port F Pull-up/Pull-down Enable Register TYPE RESET 0x(FF)FFF42A BIT 7 6 5 4 3 2 1 BIT 0 PU7 PD6 PD5 PD4 PD3 PU2 PU1 PU0 rw rw rw rw rw rw rw rw 1 1 1 1 1 1 1 1 0xFF Table 10-34.
Programming Model 10.4.8 Port G Registers Port G is comprised of the following 8-bit general-purpose I/O registers: • Port G direction register (PGDIR) • Port G data register (PGDATA) • Port G pull-up enable register (PGPUEN) • Port G select register (PGSEL) Each signal in the PGDATA register connects to an external pin. It should be noted that pins 6 and 7 are not connected to external pins. Port G provides a total of six pins, and each bit is individually configured. 10.4.8.
Programming Model PGDATA Port G Data Register BIT 7 6 TYPE 0 0 RESET 0x(FF)FFF431 5 4 3 2 1 BIT 0 D5 D4 D3 D2 D1 D0 rw rw rw rw rw rw 1 1 1 1 1 1 0x3F* *Actual bit value depends on external circuits connected to pin. Table 10-37. Port G Data Register Description Name Description Setting Reserved Bits 7–6 Reserved These bits are reserved and should be set to 0. Dx Bits 5–0 Data—These bits reflect the status of the I/O signal in an 8-bit system.
Programming Model BUSW is the default bus width for the CSA0 signal. The DTACK signal is the external input data acknowledge signal. The MC68VZ328 microprocessor will latch the BUSW signal at the rising edge of the Reset signal. Its mode will determine the default bus width for CSA0. Bit 1 is Address 0. After system reset, this signal defaults to A0. Bit 3 is HIZ/P/D (High Impedance or Program/Data).
Programming Model PGSEL Port G Select Register BIT 7 6 TYPE 0 RESET 0x(FF)FFF433 5 4 3 2 1 BIT 0 SEL5 SEL4 SEL3 SEL2 SEL1 SEL0 rw rw rw rw rw rw 0 0 1 0 0 0 0 0x08 Table 10-40. Port G Select Register Description Name Description Setting Reserved Bits 7–6 Reserved These bits are reserved and should be set to 0. SELx Bits 5–0 Select—These bits select whether the internal chip function or I/O port signals are connected to the pins.
Programming Model 10.4.9.2 Port J Data Register The bit settings for the PJDATA register are shown in Table 10-42. PJDATA TYPE Port J Data Register 0x(FF)FFF439 BIT 7 6 5 4 3 2 1 BIT 0 D7 D6 D5 D4 D3 D2 D1 D0 rw rw rw rw rw rw rw rw 1 1 1 1 1 1 1 1 RESET 0xFF* *Actual bit value depends on external circuits connected to pin. Table 10-42.
Programming Model Table 10-43. Port J Dedicated I/O Function Assignments (Continued) Bit GPIO Function Dedicated I/O Function 7 Data bit 7 CTS2 Bits 0–3 are control signals connected to SPI 1. Their operation is detailed in Section 13.2.4, “SPI 1 Signals,” on page 13-3. The remaining 4 bits are control signals for UART 2; more information appears in Section 14.2.3, “Serial Interface Signals,” on page 14-3. 10.4.9.
Programming Model 10.4.10 Port K Registers Port K is composed of the following 8-bit general-purpose I/O registers: • Port K direction register (PKDIR) • Port K data register (PKDATA) • Port K pull-up/-down enable register (PKPUEN) • Port K select register (PKSEL) Each signal in the PKDATA register connects to an external pin. As on the other ports, each bit on Port K is individually configured. 10.4.10.
Programming Model PKDATA TYPE Port K Data Register 0x(FF)FFF441 BIT 7 6 5 4 3 2 1 BIT 0 D7 D6 D5 D4 D3 D2 D1 D0 rw rw rw rw rw rw rw rw 0 0 0 0 1 1 1 1 RESET 0x0F* *Actual bit value depends on external circuits connected to pin. Table 10-47. Port K Data Register Description Name Dx Bits 7–0 Description Setting Data—These bits reflect the status of the I/O signal in an 8-bit system.
Programming Model When bit 0 is set as DATA_READY, it can be used in master mode to signal the SPI master to clock out data. PWMO2 is an output signal from the PWM 2 module. If this pin is configured as this dedicated function and PKDIR0 is set to 1, the PWMO2 signal is selected. If PKDIR0 is 0, DATA_READY is selected. This pin defaults to Port K data bit 0, GPIO input, pulled high.
Programming Model 10.4.11 Port M Registers Port M is composed of the following four general-purpose I/O registers: • Port M direction register (PMDIR) • Port M data register (PMDATA) • Port M pull-up enable register (PMPUEN) • Port M select register (PMSEL) Each signal in the PMDATA register connects to an external pin. It should be noted that pins 6 and 7 are not connected to external pins. 10.4.11.
Programming Model 10.4.11.2 Port M Data Register The settings for the PMDATA register bit positions are shown in Table 10-52. PMDATA Port M Data Register BIT 7 6 TYPE 0 0 RESET 0x(FF)FFF449 5 4 3 2 1 BIT 0 D5 D4 D3 D2 D1 D0 rw rw rw rw rw rw 1 0 0 0 0 0 0x20* *Actual bit value depends on external circuits connected to pin. Table 10-52. Port M Data Register Description Name Description Setting Reserved Bits 7–6 Reserved These bits are reserved and should be set to 0.
Programming Model 10.4.11.3 Port M Dedicated I/O Functions The six PMDATA lines are multiplexed with the dedicated I/O signals whose assignments are shown in Table 10-53. Table 10-53. Port M Dedicated I/O Function Assignments Bit GPIO Function Dedicated I/O Function 0 Data bit 0 SDCLK 1 Data bit 1 SDCE 2 Data bit 2 DQMH 3 Data bit 3 DQML 4 Data bit 4 SDA10 5 Data bit 5 DMOE 6 7 All of the dedicated I/O functions are involved in the operation of the DRAM controller.
Programming Model 10.4.11.5 Port M Select Register The select register (PMSEL) determines if a bit position in the data register (PMDATA) is assigned as a GPIO or to a dedicated I/O function. The settings for the PMSEL register bit positions are shown in Table 10-55. PMSEL Port M Select Register BIT 7 6 TYPE RESET 0 0 0x(FF)FFF44B 5 4 3 2 1 BIT 0 SEL5 SEL4 SEL3 SEL2 SEL1 SEL0 rw rw rw rw rw rw 1 1 1 1 1 1 0x3F Table 10-55.
Chapter 11 Real-Time Clock This chapter describes the real-time clock (RTC) module, which is composed of six blocks as shown in Figure 11-1: the prescaler, time-of-day (TOD) clock, TOD alarm, programmable real-time interrupt, watchdog timer, and minute stopwatch, as well as control registers and bus interface hardware. The RTC module can generate three different level 4 interrupts to the interrupt controller. The RTC can also generate a watchdog system reset.
RTC Overview 11.1 RTC Overview The prescaler uses the CLK32 clock to create a 1 Hz clock used by all of the blocks in the RTC, as shown in Figure 11-1 on page 11-2. The 1 Hz signal is used to increment the counters in the TOD clock. The TOD clock is composed of second, minute, hour, and day counters. If enabled, the TOD alarm generates an RTC interrupt when programmed alarm settings coincide with the TOD counters.
RTC Overview The prescaler stages are tapped to support real-time interrupt features. A periodic interrupt at 1 Hz is available, as well as an interrupt at the midnight rollover of the hours counter. 11.1.2 Time-of-Day Counter Although the four counters that constitute the time-of-day counter are not restricted to operation as a time-of-day counter, most designs use the counters in this fashion. The four counters (seconds, minutes, hours, and days) are toggled by the 1 Hz clock from the prescaler.
RTC Overview 11.1.4 Watchdog Timer The watchdog timer is an added check that a program is running and sequencing properly. When the application software is running, it is responsible for keeping the 2-second watchdog timer from timing out. If the watchdog timer times out, it is an indication that the software is no longer being executed in the intended sequence. At this time the watchdog timer generates either an interrupt or a reset signal to the system.
Programming Model 11.2 Programming Model Section 11.2.1, “RTC Time Register,” through Section 11.2.9, “Stopwatch Minutes Register,” provide programming information on the real-time clock. 11.2.1 RTC Time Register The real-time clock hours, minutes, and seconds (RTCTIME) register is used to program the hours, minutes, and seconds. It can be read or written at any time. After a write, the current time assumes the new values. This register cannot be reset since the real-time clock is always enabled at reset.
Programming Model 11.2.2 RTC Day Count Register The real-time clock day count register (DAYR) contains the data from the day counter. The maximum value of DAYR is 512. When the hours counter in RTCTIME reaches 23, the next time increment resets it to 00 and increments the day counter. This register can be read or written at any time. After a write, the current day assumes the new value. This register cannot be reset since it is used to keep the time.
Programming Model 11.2.3 RTC Alarm Register The real-time clock alarm (RTCALRM) register is used to configure the alarm. The hours, minutes, and seconds can be read or written at any time. After a write, the current time assumes the new values. The settings for the RTCTIME register are described in Table 11-4.
Programming Model 11.2.4 RTC Day Alarm Register The real-time clock day alarm (DAYALRM) register contains the numerical value of the day that generates the alarm. It can be read or written at any time. After a write, the current time assumes the new values. The settings for the DAYALRM register are described in Table 11-5.
Programming Model 11.2.5 Watchdog Timer Register The watchdog timer (WATCHDOG) register provides all of the control of the watchdog timer. It provides bits to enable the watchdog timer and to determine if the result of a time out is an interrupt or a system reset. The settings for the WATCHDOG register are described in Table 11-6.
Programming Model 11.2.6 RTC Control Register The real-time clock control (RTCCTL) register is used to enable the real-time clock and provide reference frequency information to the prescaler. The settings for the RTCCTL register are described in Table 11-7. RTCCTL BIT 15 RTC Control Register 14 13 12 11 10 9 8 7 6 RTCEN TYPE RESET 0 0 0 0 0 0 0 1 5 4 3 2 1 BIT 0 0 0 0 0 0 REFREQ rw 0 0x(ff)FFFB0C rw 0 0 0x0080 Table 11-7.
Programming Model RTCISR TYPE RESET RTC Interrupt Status Register BIT 15 14 13 12 11 10 9 8 RIS7 RIS6 RIS5 RIS4 RIS3 RIS2 RIS1 RIS0 rw rw rw rw rw rw rw rw 0 0 0 0 0 0 0 0 7 0 6 0 0x(ff)FFFB0E 5 4 3 2 1 BIT 0 HR 1HZ DAY ALM MIN SW rw rw rw rw rw rw 0 0 0 0 0 0 0x0000 Table 11-8. RTC Interrupt Status Register Description Name Description Setting RIS7 Bit 15 Real-Time Interrupt Status Bit 7—This bit shows the status of real-time interrupt 7.
Programming Model Table 11-8. RTC Interrupt Status Register Description (Continued) Name Description Setting MIN Bit 1 Minute Flag—If enabled, this bit is set every increment of the minute counter in the TOD clock. 0 = No 1-minute interrupt occurred. 1 = A 1-minute interrupt has occurred. SW Bit 0 Stopwatch Flag—If enabled, the stopwatch flag is set when the stopwatch minute countdown times out. 0 = The stopwatch did not time out. 1 = The stopwatch timed out. Table 11-9.
Programming Model RTCIENR RTC Interrupt Enable Register BIT 15 14 13 12 11 10 9 8 RIE7 RIE6 RIE5 RIE4 RIE3 RIE2 RIE1 RIE0 rw rw rw rw rw rw rw rw 0 0 0 0 0 0 0 0 TYPE RESET 7 0 6 0 0x(ff)FFFB10 5 4 3 2 1 BIT 0 HR 1HZ DAY ALM MIN SW rw rw rw rw rw rw 0 0 0 0 0 0 0x0000 Table 11-10. RTC Interrupt Enable Register Description Name Description Setting RIE7 Bit 15 Real-Time Interrupt Enable Bit 7—This bit enables the real-time interrupt 7.
Programming Model Table 11-10. RTC Interrupt Enable Register Description (Continued) Name Description Setting ALM Bit 2 Alarm Interrupt Enable—This bit enables the alarm interrupt. 0 = Alarm interrupt is disabled. 1 = Alarm interrupt is enabled. MIN Bit 1 Minute Interrupt Enable—This bit enables the MIN interrupt at the rate of one interrupt per minute. 0 = 1-minute interrupt is disabled. 1 = 1-minute interrupt is enabled.
Chapter 12 General-Purpose Timers This chapter describes in detail the operation of the general-purpose timer modules of the MC68VZ328. The GP timers consist of two general-purpose 16-bit timers, a prescaler, and compare and capture registers. Each timer counter value can be captured using an external event and can be configured to trigger a capture event on either the leading or trailing edges of an input pulse. The timer can also generate an interrupt when the timer reaches a programmed value.
GP Timer Overview 12.1.1 Clock Source and Prescaler The clock source for each timer is individually selectable through software. The selected clock source is fed to a prescaler that acts as a divider with a programmable division ratio ranging from 1 to 256. The output of each prescaler drives its respective counter. The clock sources are SYSCLK, SYSCLK/16, CLK32, and an external clock from the timer I/O pin (TIO).
GP Timer Overview 12.1.3 Timer Capture Register Each timer has a 16-bit capture register that takes a “snapshot” of the timer counter when a defined transition of the signal applied to the TIN pin is detected by the capture edge detector. There are three transitions of the TIN that can trigger a capture event: • Capture on rising edge • Capture on falling edge • Capture on rising or falling edge The type of transition that triggers the capture is selected by the CAP field of the TCTLx register.
GP Timer Overview 12.1.5 Cascaded Timers Both timers can be cascaded together to create a 32-bit counter. The cascade configuration is controlled by the T[1:0] field of the PCR. See Section 5.2.2, “Peripheral Control Register,” on page 5-4 for more details. Table 12-1 shows the two possible configurations of cascaded timers. When T[1:0] = 0x10, Timer 1 and Timer 2 are cascaded together. Timer 1 becomes the MSW, and Timer 2 is the LSW.
GP Timer Overview Wait on MSW No MSW status bit set? Yes Yes LSW status bit set? No Set flag 32-bit compare Figure 12-2.
Programming Model 12.2 Programming Model The following sections provide programming information about the settings of the two 16-bit timers in the GP timers module. Because the two timers are identical, the register description and the associated table describing the register settings apply to both registers. 12.2.1 Timer Control Registers 1 and 2 Each timer control (TCTLx) register controls the overall operation of its corresponding GP timer. The settings for the registers are described in Table 12-2.
Programming Model Table 12-2. Timer Control Register Description (Continued) Name CAP Bits 7–6 Description Capture Edge—This field selects the type of transition on the TIN input that triggers a capture event. Note: To use TIN/TOUT as a TIN input, ensure that the SEL6 bit in the Port B select register (PBSEL) is cleared. Setting 00 = Disable capture function (default). 01 = Capture on rising edge. 10 = Capture on falling edge. 11 = Capture on rising or falling edges.
Programming Model 12.2.2 Timer Prescaler Registers 1 and 2 Each timer prescaler register (TPRERx) controls the divide ratio of the associated prescaler. The settings for the registers are described in Table 12-3.
Programming Model 12.2.3 Timer Compare Registers 1 and 2 Each timer compare (TCMPx) register contains the value that is compared with the counter. A compare event is generated when the counter matches the value in this register. This register is set to 0xFFFF at system reset. The settings for the registers are described in Table 12-4.
Programming Model 12.2.4 Timer Capture Registers 1 and 2 Each timer capture register (TCRx) stores the counter value when a capture event occurs. The settings for the registers are described in Table 12-5.
Programming Model 12.2.5 Timer Counter Registers 1 and 2 Each read-only timer counter (TCNx) register contains the current count. The TCNx can be read at any time without affecting the current count. The settings for the registers are described in Table 12-6.
Programming Model 12.2.6 Timer Status Registers 1 and 2 Each timer status (TSTATx) register indicates the corresponding timer’s status. When a capture event occurs, it is indicated by setting the CAPT bit. When a compare event occurs, the COMP bit is set. Both bits are cleared by writing 0x0. To be cleared, these bits must first be examined, and the bit must have a value of 0x1. This ensures that an interrupt will not be missed if it occurs between the status read and when the interrupt is cleared.
Chapter 13 Serial Peripheral Interface 1 and 2 The MC68VZ328 contains two serial peripheral interface (SPI) modules, SPI 1 and SPI 2. This chapter describes the operation and programming of both SPI modules. While SPI 2 operates as a master-mode-only SPI module, SPI 1 represents an enhanced version of the SPI 2 design.
SPI 1 Operation 13.2 SPI 1 Operation The SPI 1 signal pins are multiplexed with bit 0 (DATA_READY) of the Port K register and bits 3–0 (MOSI, MISO, and SPICLK1) of the Port J register. Therefore, before SPI 1 is used, it is necessary to write 0 to these bits in the PKSEL and PJSEL registers, respectively. See Section 10.4.9.5, “Port J Select Register,” on page 10-33 and Section 10.4.10.5, “Port K Select Register,” on page 10-36 for detailed information. 13.2.
SPI 1 Operation 13.2.3 SPI 1 Phase and Polarity Configurations When SPI 1 is used as master, the SPICLK1 signal is used to transfer data in and out of the shift register. Data is clocked using any one of four programmable clock phase and polarity variations. During phase 0 operation, output data changes on the falling clock edges, and input data is shifted in on rising edges. The most significant bit is output when the CPU loads the transmitted data.
SPI 1 Programming Model 13.3 SPI 1 Programming Model This section provides information for programming SPI 1. 13.3.1 SPI 1 Receive Data Register This read-only register holds the top of the 8 × 16 RxFIFO, which receives data from an external SPI device during data transaction. The bit position assignments for this register are shown in the following register display. The settings for this register are described in Table 13-1.
SPI 1 Programming Model 13.3.2 SPI 1 Transmit Data Register This write-only data register is the top of the 8 × 16 TxFIFO. Writing to TxFIFO is permitted as long as TxFIFO is not full, even if the XCH bit is set. For example, a user may write to TxFIFO during the SPI data exchange process. In either master or slave mode, a maximum of 8 data words are loaded. Data written to this register can be of either 8-bit or 16-bit size.
SPI 1 Programming Model 13.3.3 SPI 1 Control/Status Register This register controls the configuration and operation of the SPI 1 module. The bit position assignments for this register are shown in the following register display. The settings for this register are described in Table 13-3.
SPI 1 Programming Model Table 13-3. SPI 1 Control/Status Register Description (Continued) Name Description Setting SSCTL Bit 6 SS Waveform Select—In master mode, this bit selects the output wave form for the SS signal. In slave mode, this bit controls RxFIFO advancement.
SPI 1 Programming Model 13.3.4 SPI 1 Interrupt Control/Status Register This register is used to provide interrupt control and status of various operations in SPI 1. The bit position assignments for this register are shown in the following register display. The settings for this register are described in Table 13-4.
SPI 1 Programming Model Table 13-4. SPI 1 Interrupt Control/Status Register Description (Continued) Name Description Setting TEEN Bit 8 TxFIFO Empty Interrupt Enable—This bit, when set, causes an interrupt to be generated when the TxFIFO buffer is empty and the TE bit is set. 0 = Disable TxFIFO empty interrupt. 1 = Enable TxFIFO empty interrupt.
SPI 1 Programming Model 13.3.5 SPI 1 Test Register The configurable SPI test (SPITEST) register indicates the state machine status of SPI 1 as well as the number of words currently in the TxFIFO and RxFIFO. The bit position assignments for this register are shown in the following register display. The settings for this register are described in Table 13-5.
SPI 2 Overview SPISPC SPI 1 Sample Period Control Register BIT 15 14 13 12 11 10 9 8 CSRC TYPE RESET 7 0x(FF)FFF70A 6 5 4 3 2 1 BIT 0 WAIT rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x0000 Table 13-6. SPI 1 Sample Period Control Register Description Name Description Setting CSRC Bit 15 Counter Clock Source—This bit selects the clock source for the sample period counter. 0 = SPICLK1 clock 1 = CLK32 (32.
SPI 2 Operation 13.5 SPI 2 Operation The serial peripheral interface 2 operates as a master-mode-only SPI module using a serial link to transfer data between the MC68VZ328 and a peripheral device. A chip-enable signal and a clock signal are used to transfer data between the two devices. If the external device is a transmit-only device, SPI 2’s output port is freed to be used for other purposes. See Figure 13-4.
SPI 2 Operation 13.5.1 SPI 2 Phase and Polarity Configurations The SPI 2 module uses the SPICLK2 signal to transfer data in and out of the shift register. Data is clocked using any one of four programmable clock phase and polarity variations. In phase 0 operation, output data changes on the falling clock edges and input data is shifted in on rising edges. The most significant bit is output when the CPU loads the transmitted data.
SPI 2 Programming Model 13.6 SPI 2 Programming Model This section provides information for programming SPI 2. 13.6.1 SPI 2 Data Register The SPI 2 data (SPIDATA2) register exchanges data with external slave devices. The bit position assignments for this register are shown in the following register display. The settings for this register are described in Table 13-7.
SPI 2 Programming Model 13.6.3 SPI 2 Control/Status Register The SPI 2 control/status (SPICONT2) register controls how the SPI 2 module operates and reports its status. The bit position assignments for this register are shown in the following register display. The settings for this register are described in Table 13-8.
SPI 2 Programming Model Table 13-8. SPI 2 Control/Status Register Description (Continued) Name Description Setting IRQEN Bit 6 Interrupt Request Enable—This bit enables an interrupt to be generated when an SPI 2 module exchange is finished. This bit does not affect the operation of the IRQ bit; it only affects the interrupt signal to the interrupt controller. 0 = Disable interrupt generation. 1 = Allow interrupt generation. PHA Bit 5 Phase—This bit controls the clock and data phase relationship.
Chapter 14 Universal Asynchronous Receiver/Transmitter 1 and 2 This chapter describes both UARTs in the DragonBall VZ integrated processor. The two UART ports in the MC68VZ328 may be used to communicate with external serial devices. UART 1 in the DragonBall VZ processor is identical to the UART in the DragonBall EZ processor, while UART 2 represents an enhanced version of UART 1. One of the enhancements in the UART 2 design is an enlarged RxFIFO and TxFIFO to reduce the number of software interrupts.
Serial Operation The UART 2 module is an enhanced version of the UART 1. The features listed above are enhanced by the following modifications in the UART 2 module: • The size of the RxFIFO and TxFIFO is increased to 64 bytes each. • Both the RxFIFO and TxFIFO half mark levels are user selectable. • The RTS signal can be triggered by either a near RxFIFO full condition or at the level defined by the RxFIFO level marker, rather than the RxFIFO half-full bit as is UART 1.
Stop Bit Parity Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Start Bit Serial Operation Figure 14-2. NRZ ASCII “A” Character with Odd Parity 14.2.2 IrDA Mode Stop Bit Parity Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Start Bit Infrared (IrDA) mode uses character frames as NRZ mode does, but, instead of driving ones and zeros for a full bit-time period, zeros are transmitted as three-sixteenth (or less) bit-time pulses, and ones remain low.
UART Operation • RXD1/RXD2—The Receive Data signal, which is multiplexed with PE4 (PJ4 in UART 2), is the receiver serial input. As for the TXDx pin, while the UART is in NRZ mode, standard NRZ data is expected. In IrDA mode, a pulse of at least 1.63 µs is expected for each zero bit received. The required pulse polarity is controlled by the RXPOL bit of the corresponding UART miscellaneous (UMISC) register. This pin interfaces to standard RS-232 and infrared transceiver modules.
UART Operation If the driver software has excessive interrupt service latency time, use the FIFO HALF interrupt. With UART 1, the transmitter generates an interrupt when the FIFO has fewer than 4 bytes remaining. Because UART 2 has a larger FIFO buffer, the transmitter generates an interrupt when the FIFO has a number of empty slots that is less than or equal to the number specified by the TxFIFO level marker of the FIFO level marker interrupt register.
UART Operation 14.3.2 Receiver Operation The receiver block of the UART accepts a serial data stream, converting it into parallel characters. The receiver operates in two modes—asynchronous and synchronous. In asynchronous mode, it searches for a start bit, qualifies it, and then samples the succeeding data bits at the perceived bit center. Jitter tolerance and noise immunity are provided by sampling 16 times per bit and using a voting circuit to enhance sampling. IrDA operation must use asynchronous mode.
UART Operation PRE SEL Master Clock BAUD SRC Integer Prescaler SYSCLK 0 UCLK IN 1 0 1 Non-Integer PCLK IRCLK Prescaler CLK16 1 Divide by 16 Divider n (Divide by 2 ) 0 CLK1 0 1 CLK MODE CLK SRC Figure 14-4. Baud Rate Generator Block Diagram The baud rate generator’s master clock source can be the system clock (SYSCLK), or it can be provided by the UCLK pin (input mode).
UART Operation Table 14-1. Non-Integer Prescaler Values Select (Binary) Minimum Divisor Maximum Divisor Step Size 000 2 3 127/128 1/128 001 4 7 63/64 1/64 010 8 15 31/32 1/32 011 16 31 15/16 1/16 100 32 63 7/8 1/8 101 64 127 3/4 1/4 110 128 255 1/2 1/2 111 — — — Example 14-1 provides a sample divisor calculation. Example 14-1. Sample Divisor Calculation 33.16 MHz sysclk / 1.8432 MHz for IrDA bit time = 18.0 18.
UART Operation 14.3.3.3 Integer Prescaler The baud rate generator can provide standard baud rates from many system clock frequencies. Table 14-3 contains the values that should be used in the UBAUD register for a default 33.16 MHz system clock frequency. Table 14-3.
Programming Model 14.4 Programming Model Section 14.4.1, “UART 1 Status/Control Register,” through Section 14.4.14, “FIFO Level Marker Interrupt Register,” describe the UART registers and detailed information about their settings. The UART 1 registers are described first. 14.4.1 UART 1 Status/Control Register The UART 1 status/control register (USTCNT1) controls the overall operation of the UART 1 module. The bit position assignments for this register are shown in the following register display.
Programming Model Table 14-4. UART 1 Status/Control Register Description (Continued) Name Description Setting STOP Bit 9 Stop Bit Transmission—This bit controls the number of stop bits transmitted after a character. This bit has no effect on the receiver, which expects one or more stop bits. 0 = One stop bit is transmitted 1 = Two stop bits are transmitted 8/7 Bit 8 8- or 7-Bit—This bit controls the character length.
Programming Model 14.4.2 UART 1 Baud Control Register The UART 1 baud control (UBAUD1) register controls the operation of the baud rate generator, the integer prescaler, and the UCLK signal. The bit position assignments for this register are shown in the following register display. The settings for this register are described in Table 14-5.
Programming Model 14.4.3 UART 1 Receiver Register The UART 1 receiver (URX1) register indicates the status of the receiver FIFO and character data. The FIFO status bits reflect the current status of the FIFO. At initial power up, these bits contain random data. Before enabling the receiver interrupts, the UEN and RXEN bits in the USTCNT register should be set. Reading the UART 1 receiver register initializes the FIFO status bits. The receiver interrupts can then be enabled.
Programming Model Table 14-6. UART 1 Receiver Register Description (Continued) Name Description Setting FRAME ERROR Bit 10 Frame Error (Character Status)—This read-only bit indicates that the current character had a framing error (missing stop bit), which indicates that there may be corrupted data. This bit is updated for each character read from the FIFO.
Programming Model Table 14-7. UART 1 Transmitter Register Description (Continued) Name Description Setting FIFO HALF Bit 14 FIFO Half (FIFO Status)—This read-only bit indicates that the transmitter FIFO is less than half full. This bit generates a maskable interrupt.
Programming Model 14.4.5 UART 1 Miscellaneous Register The UART 1 miscellaneous (UMISC1) register contains miscellaneous bits to control test features of the UART 1 module. Some bits, however, are only used for factory testing and should not be used. The bit position assignments for this register are shown in the following register display. The settings for this register are described in Table 14-8.
Programming Model Table 14-8. UART 1 Miscellaneous Register Description (Continued) Name Description Setting RTS1 CONT Bit 7 RTS1 Control—This bit selects the function of the RTS1 pin. 0 = RTS1 pin is controlled by the RTS1 bit. 1 = RTS1 pin is controlled by the receiver FIFO. When no more than four slots are available, RTS1 is negated. RTS1 Bit 6 Request to Send Pin—This bit controls the RTS1 pin when the RTS1 CONT bit is 0. 0 = RTS1 pin is 1. 1 = RTS1 pin is 0.
Programming Model 14.4.6 UART 1 Non-Integer Prescaler Register The UART 1 non-integer prescaler register (NIPR1) contains the control bits for the non-integer prescaler. The bit position assignments for this register are shown in the following register display. The settings for this register are described in Table 14-9.
Programming Model 14.4.7 Non-Integer Prescaler Programming Example The following steps show how to generate a 3.072 MHz clock frequency from a 16.580608 MHz clock source. 1. Calculate the divisor: divisor = 16.580608 MHz ÷ 3.072000 MHz = 5.397333 2. Find the value for the SELECT field in the NIPR. The divisor is between four and eight, so Table 14-1 on page 14-8 indicates that the SELECT field is 001. The divisor step size for the selected range is one sixty-fourth. 3.
Programming Model 14.4.8 UART 2 Status/Control Register The UART 2 status/control register (USTCNT2) controls the overall operation of the UART 2 module. The bit position assignments for this register are shown in the following register display. The settings for this register are described in Table 14-10.
Programming Model Table 14-10. UART 2 Status/Control Register Description (Continued) Name Description Setting ODEN Bit 7 Old Data Enable—This bit enables an interrupt when the OLD DATA bit in the URX register is set. 0 = OLD DATA interrupt is disabled 1 = OLD DATA interrupt is enabled CTSD Bit 6 CTS2 Delta Enable—When this bit is high, it enables an interrupt when the CTS2 pin changes state. When it is low, this interrupt is disabled. The current status of the CTS2 pin is read in the UTX register.
Programming Model 14.4.9 UART 2 Baud Control Register The UART 2 baud control (UBAUD2) register controls the operation of the baud rate generator, the integer prescaler, and the UCLK signal. The bit position assignments for this register are shown in the following register display. The settings for this register are described in Table 14-11.
Programming Model 14.4.10 UART 2 Receiver Register The UART 2 receiver (URX2) register indicates the status of the receiver FIFO and character data. The FIFO status bits reflect the current status of the FIFO. At initial power up, these bits contain random data. Before the receiver interrupts are enabled, the UEN and RXEN bits in the USTCNT register should be set. Reading the UART 2 receiver register initializes the FIFO status bits. The receiver interrupts can then be enabled.
Programming Model Table 14-12. UART 2 Receiver Register Description (Continued) Name Description Setting FRAME ERROR Bit 10 Frame Error (Character Status)—This read-only bit indicates that the current character had a framing error (missing stop bit), which indicates that there may be corrupted data. This bit is updated for each character read from the FIFO.
Programming Model Table 14-13. UART 2 Transmitter Register Description (Continued) Name Description Setting FIFO HALF Bit 14 FIFO Half (FIFO Status)—This read-only bit indicates that the transmitter FIFO is less than half full. This bit generates a maskable interrupt.
Programming Model 14.4.12 UART 2 Miscellaneous Register The UART 2 miscellaneous (UMISC2) register contains miscellaneous bits to control test features of the UART 2 module. Some bits, however, are only used for factory testing and should not be used. The bit position assignments for this register are shown in the following register display. The settings for this register are described in Table 14-14.
Programming Model Table 14-14. UART 2 Miscellaneous Register Description (Continued) Name Description Setting RTS2 CONT Bit 7 RTS2 Control—This bit selects the function of the RTS2 pin. 0 = RTS2 pin is controlled by the RTS2 bit. 1 = RTS2 pin is controlled by the receiver FIFO. When no more than four slots are available, RTS2 is negated. RTS2 Bit 6 Request to Send Pin—This bit controls the RTS2 pin when the RTS2 CONT bit is 0. 0 = RTS2 pin is 1. 1 = RTS2 pin is 0.
Programming Model 14.4.13 UART 2 Non-Integer Prescaler Register The UART 2 non-integer prescaler register (NIPR2) contains the control bits for the non-integer prescaler. The bit position assignments for this register are shown in the following register display. The settings for this register are described in Table 14-15.
Programming Model 14.4.14 FIFO Level Marker Interrupt Register The UART FIFO level marker register configures the level at which either the RxFIFO or the TxFIFO reports a half-full condition. The bit position assignments for this register are shown in the following register display. The settings for this register are described in Table 14-16.
Programming Model Table 14-17.
Chapter 15 Pulse-Width Modulator 1 and 2 This chapter describes the DragonBall VZ’s two pulse-width modulators (PWMs). Each of the pulse-width modulators has three modes of operation—playback, tone, and digital-to-analog (D/A) conversion. Using these modes, the PWM can be used to play back high-quality digital sounds, produce simple tones, or convert digital data into analog waveforms. 15.1 Introduction to PWM Operation PWM 1 uses 8-bit resolution, which is compatible with the MC68EZ328 (DragonBall EZ).
PWM 1 15.1.1 PWM Clock Signals Figure 15-2 shows a simplified block diagram of PWM 1. The prescaler and divider generate the PCLK signal from one of two clock signals—SYSCLK (the default) or CLK32. Selection of the source clock used by the pulse width modulator is made by the clock source (CLKSRC) bit in the PWM 1 control register. The CLKSEL (clock selection) field in the PWMC1 selects the frequency of the output of the divider chain.
PWM Operation 15.3 PWM Operation The pulse-width modulator has three modes of operation—playback, tone, and D/A. 15.3.1 Playback Mode In playback mode, the pulse-width modulator uses the data from a sound file to output the resulting audio through an external speaker. Although the PWM can reproduce the contents of a sound file, it is necessary to use a sampling frequency that is equal to or an even multiple of the one used to originally record the sound for the best quality reproduction.
Programming Model 15.4 Programming Model This section contains programming information about both PWM 1 and PWM 2. 15.4.1 PWM 1 Control Register This register controls the operation of the pulse-width modulator, and it also contains the status of the PWM 1 FIFO. The register bit assignments are shown in the following register display. The register settings are described in Table 15-1.
Programming Model Table 15-1. PWM 1 Control Register Description (Continued) Name Description Setting FIFOAV Bit 5 FIFO Available—This bit indicates that the FIFO is available for at least 1 byte of sample data. Data bytes can be loaded into the FIFO as long as this bit is set. If the FIFO is loaded while this bit is cleared, the write will be ignored. 0 = FIFO not available. 1 = FIFO available (default). EN Bit 4 Enable—This bit enables or disables the pulse-width modulator.
Programming Model 15.4.2 PWM 1 Sample Register This register serves as the input to the FIFO. When successive audio sample values are written to this register, they are automatically loaded into the FIFO in big-endian format. If 16-bit words are loaded, high byte is first placed into the 8-bit FIFO, and then low byte. When individual sample bytes are being written, they must be written to the low byte (SAMPLE1) only.
Programming Model 15.4.3 PWM 1 Period Register This register controls the pulse-width modulator period. When the counter value matches PERIOD + 1, the counter is reset to start another period. Therefore, the following equation applies: Eqn. 15-1 PWMO (Hz) = PCLK (Hz) / (PERIOD + 2) Writing 0xFF to this register achieves the same result as writing 0xFE. The register bit assignments are shown in the following register display. The register settings are described in Table 15-3.
PWM 2 15.5 PWM 2 PWM 2 is a 16-bit PWM module that is compatible with the one used in the original DragonBall processor, MC68328. Besides the difference in the PWM code size (8-bit versus 16-bit), the major difference between PWM 2 and PWM 1 is that PWM 2 does not have a data FIFO. Figure 15-4 illustrates the block diagram of the pulse-width modulator unit 2. Width Compare SYSCLK Prescaler Output Control Counter PWMO Period Compare Figure 15-4. PWM 2 Block Diagram 15.5.
PWM 2 Table 15-5. PWM 2 Control Register Description (Continued) Name Description Setting PIN Bit 7 Pin Status Indicator—This bit indicates the current status of the PWM. 0 = PWM output is high. 1 = PWM output is low. Reserved Bit 6 Reserved This bit is reserved and should be set to 0. POL Bit 5 Output Polarity—This bit controls the PWM output polarity. 0 = Normal polarity. 1 = Inverted polarity. PWMEN Bit 4 PWM Enable—This bit enables PWM 2. 0 = PWM 2 disabled. 1 = PWM 2 enabled.
PWM 2 15.5.3 PWM 2 Pulse Width Register This register controls the pulse width of PWM 2. The register bit assignments are shown in the following register display. The register settings are described in Table 15-7. PWMW2 PWM 2 Pulse Width Control Register BIT 15 14 13 12 11 10 9 8 0x(FF)FFF514 7 6 5 4 3 2 1 BIT 0 WIDTH TYPE RESET rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x0000 Table 15-7.
Chapter 16 In-Circuit Emulation This chapter describes the in-circuit emulation (ICE) module of the MC68VZ328 and provides detailed information about its operation and registers. The ICE module is designed to support low-cost emulator designs using the MC68VZ328 microprocessor. Using four interface signals that are extended to external pins, the ICE module has access to the 68000 CPU resources, with minimal restrictions.
ICE Operation 16.1 ICE Operation The in-circuit emulation module’s operation consists of the following tasks: • Entering emulation mode • Detecting breakpoints • Using the signal decoder • Using the interrupt gate module • Using the A-line insertion unit 16.1.1 Entering Emulation Mode The in-circuit emulation module latches the state of the EMUIRQ signal on the rising edge of the RESET signal.
ICE Operation 16.1.2.1 Execution Breakpoints vs. Bus Breakpoints An execution breakpoint is a breakpoint at which the current program execution stops and gives control to the monitor. To set up a single execution breakpoint, initialize the compare and mask registers; set the SB, PBEN, and CEN bits in the in-circuit emulation module control register (ICEMCR); and then clear the BBIEN and HMDIS bits in the same register. For multiple execution breakpoint mode, clear the SB bit.
Programming Model 16.2 Programming Model This section contains information about the ICE registers and programming information about their settings. 16.2.1 In-Circuit Emulation Module Address Compare and Mask Registers The in-circuit emulation module address compare register (ICEMACR) is used to store the address of the breakpoint, and the in-circuit emulation module address mask register (ICEMAMR) is used to mask the corresponding address bit in the ICEMACR.
Programming Model ICEMACR TYPE RESET TYPE RESET ICE Module Address Compare Register BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 BIT 16 AC3 1 AC 30 AC2 9 AC2 8 AC2 7 AC2 6 AC 25 AC 24 AC 23 AC 22 AC 21 AC 20 AC 19 AC 18 AC 17 AC16 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x0 BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 BIT 0 AC1 5 AC 14 AC1 3 AC1 2 AC1 1 AC1 0 AC 9 AC 8 AC 7 A
Programming Model 16.2.2 In-Circuit Emulation Module Control Compare and Mask Register The in-circuit emulation module control compare (ICEMCCR) register is used to set the breakpoint at a specific bus cycle, and the in-circuit emulation module control mask register (ICEMCMR) is used to mask the corresponding control bit in the ICEMCMR.
Programming Model Table 16-3. ICE Control Mask Register Description (Continued) Name Description Setting RWM Bit 1 Read or Write Cycle Mask—This bit masks the RW bit of the ICEMCCR. 0 = Enable the comparator to compare itself against the RW bit. 1 = Force a true comparison (“don’t care”) on the corresponding bit. PDM Bit 0 Program or Data Cycle Mask—This bit masks the PD bit of the ICEMCCR. 0 = Enable the comparator to compare itself against the PD bit.
Programming Model 16.2.3 In-Circuit Emulation Module Control Register The in-circuit emulation module control register (ICEMCR) is used to control the in-circuit emulation module. The bit assignments for the ICE module control register are shown in the following register display. The settings for the bits are described in Table 16-4.
Programming Model Table 16-4. ICE Module Control Register Description (Continued) Name CEN Bit 0 Description Setting Compare Enable—This bit is used to activate the comparison logic. It is recommended that the address compare and mask registers be programmed before setting this bit to valid. 0 = Disable the breakpoint comparison logic. 1 = Enable the breakpoint comparison logic. Table 16-5.
Typical Design Programming Example 16.2.4 In-Circuit Emulation Module Status Register The in-circuit emulation module status register (ICEMSR) is used to determine the source of an interrupt. The bit assignments for the ICE module status register are shown in the following register display. The settings for the bits are described in Table 16-6.
Typical Design Programming Example Select/Control PC MOCLK Host Control BUSW CSxx Address Comparator FPGA for More Hardware Breakpoint Expansion (Optional) Select/control EMUBRK EMUCS A[23:0] EMUIRQ MC68VZ328 CPU CS MAP FPGA CS CSxx 3.3 V / 5 V Buffer Debug ROM Emulation Memory 4M Maximum (Optional) DTACK D[15:0] D[15:0] P/D D[15:0] MC68VZ328 Bus CLKO Optional Trace Module Solder-on Emulator Pod Footprint Target Board Figure 16-2. Typical Emulator Design Example 16.3.
Plug-in Emulator Design Example 16.3.3 Emulation Memory Mapping FPGA and Emulation Memory Since the memory on the target board may not be fully built or debugged, it is necessary to have some memory that replaces the target memory for debugging at the initial stage. In some cases, ROM codes are downloaded to a shadowed RAM area for debugging purposes. The map FPGA will work with those chip-select signals to map them to the emulation memory, instead of going directly to the target board. 16.3.
Plug-in Emulator Design Example Emulation Module RS-232/ADI PC Host Interface 68HC681 or ADI EMUCS PAL /3.3 V /5 V Buffer A[15:14] EMUIRQ DTACK MC68VZ328 CPU 16K Debug ROM CSxx 16K Debug SRAM On-Board Memory RAM/ROM 3.3 V to 5 V Buffer D[15:0] D[15:0] D[15:8] / A[13:0] Figure 16-3. Plug-in Emulator Design Example Although there is only one hardware breakpoint in this design, all other software breakpoints can be generated by replacing the memory content of the A0 instruction.
Application Development Design Example 16.5 Application Development Design Example Figure 16-4 displays an example of an application development system design. This example is for initial start-up designs and software development that occurs after the target hardware system is completed. 1M VDD 10K 1N4148 Reset Switch 1M TR VDD 0.47 µ R CV 0.1 µ 10K Q DIS THR MC1455 0.
Chapter 17 Bootstrap Mode This chapter describes the operation and programming information of the bootstrap mode of the MC68VZ328. The bootstrap mode is designed to allow the initialization of a target system and the ability to download programs or data to the target system RAM using either the UART 1 or UART 2 controller. See Chapter 14, “Universal Asynchronous Receiver/Transmitter 1 and 2,” for information on operating and programming the UART controllers.
Bootstrap Mode Operation 17.1.1 Entering Bootstrap Mode Bootstrap mode is one of the three operation modes (normal, emulation, and bootstrap) of the MC68VZ328. Of the three modes, bootstrap has the highest priority. To enter bootstrap mode, the EMUBRK signal must be driven low and a system reset must be performed. After reset, bootstrap reset vectors are internally generated for reset vector fetch cycles. Figure 17-1 illustrates bootstrap mode reset vector fetch timing.
Bootstrap Mode Operation 17.1.3 Setting Up the RS-232 Terminal To set up communication between your target system and the PC, set the communication specifications to 19,200 bps, no parity, 8-bit, and 1 stop bit. It is permissible to pause after each line (b-record) is transferred to ensure that each transferred ASCII character is echoed. After the hardware is set up, the system is powered up, and bootstrap mode is entered, sending any ASCII character to the target system will initiate the link.
Bootstrap Mode Operation 17.1.5 System Initialization Programming Example Before downloading a program to system memory, the target system may need to be initialized using the internal registers. An init file can be built using a text editor. Example 17-1 is an initialization file for the MC68VZ328ADS board. Example 17-1. System Initialization Programming Example ************************************************* * init.
Bootstrap Mode Operation 17.1.6 Application Programming Example The code shown in Example 17-2 can be used to calculate a CRC value. The example demonstrates how assembly code is assembled and downloaded to system RAM. Example 17-2. Application Programming Example section code START: copy clr.l d1 clr.w d2 nextwd move.w (a0,d2),d6 move.w d6,(a1)+ add.l #2,d1 add.w #2,d2 cmpi.w #16,d2 blt nextwd clr.w d2 cmp.l d0,d1 blt nextwd crc lp2 ;d1 is used to count the number of words copied.
Bootloader Flowchart 17.1.7 Example of Instruction Buffer Usage Example 17-3 demonstrates how to run a 68000 instruction using the instruction buffer. Example 17-3. Using Instruction Buffers ORG.L $FFFFFFC0 move.
Bootloader Flowchart Start Test receive FIFO; Initialize appropriate UART Receive a bootstrap record NO CNT = 0? Store DATA to ADDR YES YES ADDR = IBUFF? Execute instruction in IBUFF NO Run program starting at ADDR Figure 17-2.
Special Notes 17.3 Special Notes The following information may be useful when the MC68VZ328 is in bootstrap mode. • A b-record is a string of uppercase hex characters with optional comments that follow. • Comments in a b-record or b-record file must not contain any word or symbol that is longer than nine characters.
Chapter 18 Application Guide This chapter contains helpful information that will assist with integrating the MC68VZ328 into new or existing designs. It includes a design checklist and instructions for using the MC68VZ328 Application Development System (ADS) board to get the design process started as quickly as possible. 18.1 Design Checklist When the MC68VZ328 microprocessor is being integrated into an application, the following items can be used as guides during the design process.
Application Guide 18.1.3 Clock and Layout Considerations This section covers layout considerations affecting DragonBall timing issues during operation and also during the initial power up. • Place the crystal within 0.5 inches of the MC68VZ328. The crystal and the capacitors must be as close to the chip as possible. • If an RC reset circuit is being used, place the resistor and capacitor within 0.5 inches of the MC68VZ328. The RESET pin is a Schmitt trigger input signal.
Chapter 19 Electrical Characteristics This chapter documents electrical characteristics and provides timing information necessary to design systems using the MC68VZ328 microprocessor. Section 19.2, “DC Electrical Characteristics,” provides detailed information about both maximum and minimum DC characteristics of the MC68VZ328. Section 19.3, “AC Electrical Characteristics,” consists of output delays, input setup and hold times, and signal skew times.
AC Electrical Characteristics 19.2 DC Electrical Characteristics Table 19-2 contains both maximum and minimum DC characteristics of the MC68VZ328. Table 19-2. Maximum and Minimum DC Characteristics Number or Symbol (3.0 ± 0.3) V Characteristic Unit Minimum Typical Maximum 1 Full running operating current at 33 MHz — 20 40 mA 2 Standby current1 — 35 60 µA VIH Input high voltage 0.7 VDD — — V VIL Input low voltage — — 0.4 V VOH Output high voltage (IOH = 2.0 mA) 0.
AC Electrical Characteristics S4 S2 S0 WS S6 S0 CLKO 1 2 CSx 3 4 RASx 5 6 CASx Figure 19-1. CLKO Reference to Chip-Select Signals Timing Diagram Table 19-3. CLKO Reference to Chip-Select Signals Timing Parameters (3.0 ± 0.
AC Electrical Characteristics A[31:0] 1 6 CSx 2 UWE/LWE 3 9 OE 4 8 D[15:0] 5 7 DTACK UDS/LDS 10 11 UB/LB Figure 19-2. Chip-Select Read Cycle Timing Diagram Table 19-4. Chip-Select Read Cycle Timing Parameters (3.0 ± 0.
AC Electrical Characteristics Table 19-4. Chip-Select Read Cycle Timing Parameters (Continued) (3.0 ± 0.3) V Number 11 Characteristic Unit Minimum Maximum 10 — CSx negated to UB/LB negated (16-bit SRAM) ns Note: n is the number of wait states in the current memory access cycle. T is the system clock period. The external DTACK input requirement is eliminated when CSx is programmed to use internal DTACK. CSx stands for CSA0, CSA1, CSB0, CSB1, CSC0, CSC1, CSD0, or CSD1.
AC Electrical Characteristics Table 19-5. Chip-Select Write Cycle Timing Parameters (3.0 ± 0.
AC Electrical Characteristics A[31:0] 1 5 CSx 2 6 UWE/LWE OE 9 3 8 D[15:0] 4 7 DTACK Figure 19-4. Chip-Select Flash Write Cycle Timing Diagram Table 19-6. Chip-Select Flash Write Cycle Timing Parameters (3.0 ± 0.
AC Electrical Characteristics 19.3.5 Chip-Select Timing Trim Figure 19-5 shows the timing diagram for the chip-select timing trim. The signal values and units of measure for this figure are found in Table 19-7. For detailed information about the individual signals, see Chapter 6, “Chip-Select Logic.” S0 S4 S2 WS S6 S0 CLKO 1 CSx 2 CSx 3 UWE/LWE 4 UWE/LWE Figure 19-5. Chip-Select Timing Trim Timing Diagram Table 19-7. Chip-Select Timing Trim Timing Parameters (3.0 ± 0.
AC Electrical Characteristics MD[12:0] Row 1 Column 4 Row 12 14 5 RASx 6 CASx 8 13 2 7 DWE 3 11 OE 9 10 D[15:0] Figure 19-6. DRAM Read Cycle 16-Bit Access (CPU Bus Master) Timing Diagram Table 19-8. DRAM Read Cycle 16-Bit Access (CPU Bus Master) Timing Parameters (3.0 ± 0.
AC Electrical Characteristics Table 19-8. DRAM Read Cycle 16-Bit Access (CPU Bus Master) Timing Parameters (Continued) (3.0 ± 0.3) V Number Characteristic Unit Minimum Maximum 12 CASx asserted before column address invalid 50 — ns 13 RASx negated after CASx is negated 28 — ns 14 RASx precharge time (SLW= 0,1) 58,118 — ns Note: RASx stands for RAS0 and RAS1. CASx stands for CAS0 and CAS1. Note: MSW is bit 5, SLW is bit 3, and BC[1:0] comprises bits 13–12 in the DRAMC register.
AC Electrical Characteristics Table 19-9. DRAM Write Cycle 16-Bit Access (CPU Bus Master) Timing Parameters (3.0 ± 0.
AC Electrical Characteristics 1 5 CASx 3 2 4 RASx 6 DWE Figure 19-8. DRAM Hidden Refresh Cycle (Normal Mode) Timing Diagram Table 19-10. DRAM Hidden Refresh Cycle (Normal Mode) Timing Parameters (3.0 ± 0.
AC Electrical Characteristics Table 19-11. DRAM Hidden Refresh Cycle (Low-Power Mode) Timing Parameters (3.0 ± 0.3) V Number Characteristic Unit Minimum Maximum 1 CASx pulse width 120 — ns 2 RASx pulse width 120 — ns 3 CASx asserted to RASx asserted 30 — ns 4 CASx negated to RASx negated 30 — ns 5 Refresh cycle (using 32.768 KHz crystal) 15 — us 5 Refresh cycle (using 38.
AC Electrical Characteristics Table 19-12. LCD SRAM/ROM DMA Cycle 16-Bit Mode Access Timing Parameters (3.0 ± 0.3) V Number Characteristic Unit Minimum Maximum 1 Address valid to CSx asserted 20 — ns 2 UWE/LWE to CSx asserted 28 — ns 3 Data setup time 16 — ns 4 CLKO to address valid — 10 ns 5 CLKO high to CSx — 10 ns 19.3.
AC Electrical Characteristics Table 19-13. LCD DRAM DMA Cycle 16-Bit EDO RAM Mode Access (LCD Bus Master) Timing Parameters (3.0 ± 0.
AC Electrical Characteristics 19.3.12 LCD DRAM DMA Cycle 16-Bit Fast Page Mode Access (LCD Bus Master) Figure 19-12 shows the timing diagram for the LCD DRAM DMA cycle for 16-bit Fast Page Mode mode access (LCD bus master). The signal values and units of measure for this figure are found in Table 19-14. Detailed information about the operation of individual signals can be found in Chapter 7, “DRAM Controller,” and Chapter 8, “LCD Controller.
AC Electrical Characteristics Table 19-14. LCD DRAM DMA Cycle 16-Bit Fast Page Mode Access (LCD Bus Master) Timing Parameters (Continued) (3.0 ± 0.
AC Electrical Characteristics Self-Refresh Mode LFLM LLP LD[7:0] LREF LCLK Figure 19-14. LCD Controller Timing Diagram (Self-Refresh Mode) Table 19-15. LCD Controller Timing Parameters (3.0 ± 0.
AC Electrical Characteristics 19.3.14 Page-Miss SDRAM CPU Read Cycle (CAS Latency = 1) Figure 19-15 shows the timing diagram for the page-miss SDRAM CPU read cycle. The signal values and units of measure for this figure are found in Table 19-16 on page 19-31. Detailed information about the operation of individual signals can be found in both Chapter 8, “LCD Controller,” and Chapter 7, “DRAM Controller.
AC Electrical Characteristics 19.3.15 Page-Hit SDRAM CPU Read Cycle (CAS Latency = 1) Figure 19-16 shows the timing diagram for the page-hit SDRAM CPU read cycle. The signal values and units of measure for this figure are found in Table 19-16 on page 19-31. Detailed information about the operation of individual signals can be found in both Chapter 8, “LCD Controller,” and Chapter 7, “DRAM Controller.
AC Electrical Characteristics 19.3.16 Page-Hit CPU Read Cycle for 8-Bit SDRAM (CAS Latency = 1) Figure 19-17 shows the timing diagram for the page-hit CPU read cycle for 8-bit SDRAM. The signal values and units of measure for this figure are found in Table 19-16 on page 19-31. Detailed information about the operation of individual signals can be found in both Chapter 8, “LCD Controller,” and Chapter 7, “DRAM Controller.
AC Electrical Characteristics 19.3.17 Page-Miss SDRAM CPU Write Cycle (CAS Latency = 1) Figure 19-18 shows the timing diagram for the page-miss SDRAM CPU write cycle for 8-bit SDRAM. The signal values and units of measure for this figure are found in Table 19-16 on page 19-31. Detailed information about the operation of individual signals can be found in both Chapter 8, “LCD Controller,” and Chapter 7, “DRAM Controller.
AC Electrical Characteristics 19.3.18 Page-Hit SDRAM CPU Write Cycle (CAS Latency = 1) Figure 19-19 shows the timing diagram for the page-hit SDRAM CPU write cycle for 8-bit SDRAM. The signal values and units of measure for this figure are found in Table 19-16 on page 19-31. Detailed information about the operation of individual signals can be found in both Chapter 8, “LCD Controller,” and Chapter 7, “DRAM Controller.
AC Electrical Characteristics 19.3.19 Page-Hit CPU Byte-Write Cycle for 8-Bit SDRAM (CAS Latency = 1) Figure 19-20 shows the timing diagram for the page-hit SDRAM CPU byte-write cycle for 8-bit SDRAM. The signal values and units of measure for this figure are found in Table 19-16 on page 19-31. Detailed information about the operation of individual signals can be found in both Chapter 8, “LCD Controller,” and Chapter 7, “DRAM Controller.
AC Electrical Characteristics 19.3.20 Page-Hit CPU Read Cycle in Power-down Mode (CAS Latency = 1, Bit APEN of SDRAM Power-down Register = 1) Figure 19-21 shows the timing diagram for the page-hit CPU read cycle in power-down mode. The signal values and units of measure for this figure are found in Table 19-16 on page 19-31. Detailed information about the operation of individual signals can be found in both Chapter 8, “LCD Controller,” and Chapter 7, “DRAM Controller.
AC Electrical Characteristics 19.3.21 Exit Self-Refresh Due to CPU Read Cycle (CAS Latency = 1, Bit RM of DRAM Control Register = 1) Figure 19-22 shows the timing diagram for the exit self-refresh due to the CPU read cycle. The signal values and units of measure for this figure are found in Table 19-16 on page 19-31. Detailed information about the operation of individual signals can be found in both Chapter 8, “LCD Controller,” and Chapter 7, “DRAM Controller.
AC Electrical Characteristics 19.3.22 Enter Self-Refresh Due to No Activity for 64 Clocks (Bit RM of DRAM Control Register = 1) Figure 19-23 shows the timing diagram for enter self-refresh due to no activity. The signal values and units of measure for this figure are found in Table 19-16 on page 19-31. Detailed information about the operation of individual signals can be found in both Chapter 8, “LCD Controller,” and Chapter 7, “DRAM Controller.
AC Electrical Characteristics 19.3.23 Page-Miss at Starting of LCD DMA for SDRAM (CAS Latency = 1) Figure 19-24 shows the timing diagram for the page-miss at the starting of LCD DMA for SDRAM. The signal values and units of measure for this figure are found in Table 19-16 on page 19-31. Detailed information about the operation of individual signals can be found in both Chapter 8, “LCD Controller,” and Chapter 7, “DRAM Controller.
AC Electrical Characteristics 19.3.24 Page-Miss at Start and in Middle of LCD DMA (CAS Latency = 1) Figure 19-25 shows the timing diagram for the page-miss at the start and in the middle of LCD DMA. The signal values and units of measure for this figure are found in Table 19-16 on page 19-31. Detailed information about the operation of individual signals can be found in both Chapter 8, “LCD Controller,” and Chapter 7, “DRAM Controller.
AC Electrical Characteristics 19.3.25 Page-Hit LCD DMA Cycle for SDRAM (CAS Latency = 1) Figure 19-26 shows the timing diagram for the page-hit LCD DMA cycle for SDRAM. The signal values and units of measure for this figure are found in Table 19-16 on page 19-31. Detailed information about the operation of individual signals can be found in both Chapter 8, “LCD Controller,” and Chapter 7, “DRAM Controller.
AC Electrical Characteristics Table 19-16. Timing Parameters for Figure 19-15 Through Figure 19-26 (3.0 ± 0.
AC Electrical Characteristics 19.3.26 SPI 1 and SPI 2 Generic Timing Figure 19-27 shows the timing diagram for SPI 1 and SPI 2. The signal values and units of measure for Figure 19-27 through Figure 19-32 are found in Table 19-17 on page 19-34. Detailed information about the operation of individual signals can be found in Chapter 13, “Serial Peripheral Interface 1 and 2.
AC Electrical Characteristics 19.3.28 SPI 1 Master Using DATA_READY Level Trigger Figure 19-29 shows the timing diagram for the SPI 1 master using the DATA_READY level trigger. The signal values and units of measure for Figure 19-27 through Figure 19-32 are found in Table 19-17 on page 19-34. Detailed information about the operation of individual signals can be found in Chapter 13, “Serial Peripheral Interface 1 and 2.” SS (Output) DATA_READY (Input) SCLK, MOSI, MISO Figure 19-29.
AC Electrical Characteristics 19.3.31 SPI 1 Slave FIFO Advanced by SS Rising Edge Figure 19-32 shows the timing diagram for the SPI 1 slave FIFO advanced by SS rising edge. The signal values and units of measure for Figure 19-27 through Figure 19-32 are found in Table 19-17. Detailed information about the operation of individual signals can be found in Chapter 13, “Serial Peripheral Interface 1 and 2.” 10 SS (Input) 9 SCLK, MOSI, MISO 11 Figure 19-32.
AC Electrical Characteristics 19.3.32 Normal Mode Timing Figure 19-33 shows the timing diagram for normal mode timing of the MC68VZ328. The signal values and units of measure for Figure 19-33 through Figure 19-35 are found in Table 19-18 on page 19-36. RESET 1 2 EMUIRQ EMUBRK HIZ Figure 19-33. Normal Mode Timing Diagram 19.3.33 Emulation Mode Timing Figure 19-34 shows the timing diagram for emulation mode timing of the MC68VZ328.
AC Electrical Characteristics 19.3.34 Bootstrap Mode Timing Figure 19-35 shows the timing diagram for bootstrap mode timing of the MC68VZ328. The signal values and units of measure for Figure 19-33 through Figure 19-35 are found in Table 19-18. RESET 1 2 EMUIRQ EMUBRK HIZ Figure 19-35. Bootstrap Mode Timing Diagram Table 19-18. Timing Parameters for Figure 19-33 Through Figure 19-35 (3.0 ± 0.
Chapter 20 Mechanical Data and Ordering Information This chapter provides mechanical data, including illustrations, and ordering information. 20.1 Ordering Information Table 20-1 provides ordering information for the two package types: the 144-lead, plastic, thin quad flat package (TQFP) and the 144-lead mold array process ball grid array (MAPBGA) package. Table 20-1.
TQFP Pin Assignments 20.
TQFP Package Dimensions 20.3 TQFP Package Dimensions Figure 20-2 illustrates the TQFP 20 mm × 20 mm package, which has 0.5 mm spacing between the pads. The device designator for the TQFP package is PV. 0.20 T L-M N 4X PIN 1 IDENT 0.20 T L-M N 4X 36 TIPS 109 144 1 108 4X J1 P J1 L M C L B V X X=L, M OR N 140X B1 V1 VIEW Y 36 G VIEW Y 73 37 NOTES: 1. DIMENSIONS AND TOLERANCING PER ASME Y14.5M, 1994. 2. DIMENSIONS IN MILLIMETERS. 3.
MAPBGA Pin Assignments 20.4 MAPBGA Pin Assignments Figure 20-3 provides a top view of the MAPBGA pin assignments.
MAPBGA Package Dimensions 20.5 MAPBGA Package Dimensions Figure 20-4 illustrates the MAPBGA 13 mm × 13 mm package, which has 1 mm spacing between the pads. The device designator for the MAPBGA package is VF. D X DETAIL K LASER MARK FOR PIN 1 IDENTIFICATION IN THIS AREA M NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DIMENSION b IS MEASURED AT THE MAXIMUM SOLDER BALL DIAMETER, PARALLEL TO DATUM PLANE Z. 4.
PCB Finish Requirement 20.6 PCB Finish Requirement For a more reliable BGA assembly process, use HASL finish on PCB. EMNI AU finish is not recommended. When EMNI AU finish is used on PCB, brittle intermetallic fractures occasionally occur at the BGA pad–to–PCB pad solder joint.
Index Numerics B 16-Bit SRAM enable bit, see SR16 bit 32-bit counter, see cascaded timers 8- or 7-bit bit, see 8/7 bit 8/7 bit USTCNT1 register, 14-11 USTCNT2 register, 14-20 Baud rate generator baud rates affected by PLL frequencies, 14-9 block diagram, 14-7 divider, binary, 14-7 divisor calculation, 14-8 non-integer prescaler, 14-7 operation, 14-6 reset bit, see BAUD RESET bit testing bit, see BAUD TEST bit BAUD RESET bit UMISC1 register, 14-16 UMISC2 register, 14-26 Baud source bit, see BAUDSRC bit BA
reset timing diagram, 17-2 setting up RS-232 terminal, 17-3 Break (character status) bit, see BREAK bit BREAK bit URX1 register, 14-14 URX2 register, 14-24 Break characters, generating, 14-5 BSW bit CSA register, 6-8 CSB register, 6-10 CSC register, 6-12 CSD register, 6-15 BUPS2 bit, 6-18 Burst mode during wake-up event, 4-13 operation, 4-12 operational example, 4-13 setting the PEN bit, effects of, 4-11 Bus control signals bus width, see BUSW/DTACK/PG0 pin data strobe signals, see UDS/PK3, LDS/PK2 pin data
CLK32 bit, 4-10 CLK32 clock signal crystal frequency range, 4-4 crystal oscillator circuit example, 4-4 crystal ramp-up time, 4-4 description, 4-4 CLKEN bit, 4-8 CLKM bit USTCNT1 register, 14-10 USTCNT2 register, 14-20 CLKO/PF2 pin, 2-4 CLKSEL field PWMC1 register, 15-5 PWMC2 register, 15-9 CLKSOURCE field TCTL1 register, 12-7 TCTL2 register, 12-7 CLKSRC bit PWMC1 register, 15-4 UMISC1 register, 14-16 UMISC2 register, 14-26 Clock bit, see CLK bit Clock enable bit, see CLKEN bit Clock generation module (CGM)
CTSD bit USTCNT1 register, 14-11 USTCNT2 register, 14-21 CTSx pin, programming to post interrupt, 14-3 CUPS2 bit, 6-18 Cursor control 1 and 0 field, see CCx field Cursor height 4–0 field, see CHx field Cursor vertical Y pixel 8–0 field, see CYPx field Cursor width 4–0 field, see CWx field Cursor X position 9–0 field, see CXPx field CWSO bit, 6-17 CWx field, 8-14 CXPx field, 8-13 CYPx field, 8-13 D D[15:8] pins, 2-5 D[7:0]/PA[7:0] pins, 2-5 Data and address mode types, see CPU Data b-record format, see boot
PCDATA register, 10-12 PDDATA register, 10-17 PEDATA register, 10-22 PFDATA register, 10-25 PGDATA register, 10-29 PJDATA register, 10-32 PKDATA register, 10-35 PMDATA register, 10-38 E Early ASB delay processing for static memory early detection bit, see EASP bit Early ASB delay value field, see EASDLY[1:0] field Early cycle detection for dynamic memory bit, see ECDD bit Early cycle detection for static memory bit, see ECDS bit Early cycle detection type bit, see ECDT bit EASDLY[1:0] field, 6-19 EASP bit,
Frame marker polarity bit, see FLMPOL bit Frame rate modulation, absence of control function, 8-7 Free-running/restart bit, see FRR bit FRR bit, 12-6 Full address decode enable bit, see UGEN bit G G13–G10 field, 8-20 G23–G20 field, 8-20 GBAx field, 6-4 GBBx field, 6-5 GBCx field, 6-5 GBDx field, 6-6 General-purpose timers, see GP timers GP timers block diagram, 12-1 changing clock source, precautions, 12-2 clock sources, 12-2 description, 12-1 events capture events, 12-2 compare events, 12-2 interrupt even
ICEMCR register, 16-8 ICEMSR register, 16-10 ICR register, 9-8 Ignore CTS1 (Tx control) bit, see NOCTS1 bit Ignore CTS2 (Tx control) bit, see NOCTS2 bit ILCR register, 9-19 IMR register, 9-10 In-circuit emulation module, see ICE module Infrared enable bit, see IRDAEN bit Infrared testing bit see IRTEST bit Infrared, see IrDA INT[3:0] pins, 2-6 INT0 bit IPR register, 9-18 ISR register, 9-14 INT1 bit IPR register, 9-18 ISR register, 9-14 INT2 bit IPR register, 9-18 ISR register, 9-14 INT3 bit IPR register, 9-
ISR register, 9-13 IRQ6/PD[7:0] pin, 2-6 IRQEN bit PWMC1 register, 15-4 PWMC2 register, 15-8 SPICONT2 register, 13-16 TCTL1 register, 12-7 TCTL2 register, 12-7 IRTEST bit UMISC1 register, 14-16 UMISC2 register, 14-26 ISR register, 9-12 IVR register, 9-7 K KB bit IPR register, 9-18 ISR register, 9-14 KBENx field, 10-20 Keyboard enable field, see KBENx field Keyboard interrupt request bit, see KB bit KPUEN register, 10-36 L LACD/PC7 pin, 2-7 LACDRC register, 8-17 LBLKC register, 8-15 LCD alternate crystal d
LCD screen width register, see LXMAX register LCD self-refresh on bit, see REF_ON bit LCD shift clock polarity bit, see LCKPOL bit LCD source field for PWM counter, see SRC1-0 field LCD SRAM/ROM DMA cycle 16-bit mode access timing (1 wait state), 19-13 LCD virtual page width field, see VPx field LCDCLK SEL field, 4-8 LCDON bit, 8-18 LCKCON register, 8-18 LCKPOL bit, 8-16 LCLK/PC6 pin, 2-7 LCONTRAST/PF0 pin, 2-8 LCWCH register, 8-14 LCWS bit, 6-20 LCXP register, 8-12 LCYP register, 8-13 LD[3:0]/PC[3:0], LD[7
MUART1 bit, 9-11 MUART2 bit, 9-11 multiplexing options for SDRAM, selecting, 7-5 to 7-6 MWDT bit, 9-11 N NIPR1 register, 14-18 NIPR2 register, 14-28 NOCTS1 bit, 14-15 NOCTS2 bit, 14-25 Nonreturn to zero mode, see NRZ mode Normal mode definition, 4-11 timing, 19-35 NRZ mode, 14-2 O ODD bit USTCNT1 register, 14-10 USTCNT2 register, 14-20 Odd parity bit, see ODD bit ODEN bit USTCNT1 register, 14-11 USTCNT2 register, 14-21 OE pin, 2-6 Old data (FIFO status) bit, see OLD DATA bit OLD DATA bit URX1 register, 14
PGSZ field, 7-14 PHA bit SPICONT1 register, 13-7 SPICONT2 register, 13-16 Phase bit, see PHA bit Phase-locked loop, see PLLCLK output frequency PIN bit, 15-9 Pin status indicator bit, see PIN bit Pixel clock divider 5–0 field, see PCDx field Pixel offset code field, see POSx field Pixel polarity bit, see PIXPOL bit PIXPOL bit, 8-16 PJDATA register, 10-32 PJDIR register, 10-31 PJPUEN register, 10-33 PJSEL register, 10-33 PKDATA register, 10-35 PKDIR register, 10-34 PKPUEN register, 10-36 PKSEL register, 10-3
bit 4, see RXD1/PE4 pin bit 5, see TXD1/PE5 pin bit 6, see RTS1/PE6 pin dedicated I/O functions, 10-22 registers data register, see PEDATA register direction register, see PEDIR register pull-up enable register, see PEPUEN register register summary, 10-21 select register, see PESEL register Port F bit 0, see LCONTRAST/PF0 pin bit 2, see CLKO/PF2 pin dedicated I/O functions, 10-25 registers data register, see PFDATA register direction register, see PFDIR register pull-up enable register, see PFPUEN register
interrupt controller, 9-7 to 9-19 LCD controller, 8-10 to 8-22 PWM 1, 15-4 to 15-7 PWM 2, 15-8 to 15-10 SPI 1, 13-4 to 13-11 SPI 2, 13-14 to 13-16 system control, 5-2 to 5-6 UARTs, 14-10 to 14-30 PROT bit, 4-10 Protect bit bit, see PROT bit Pull-down field, see PDx field Pull-down resistors, see I/O ports Pull-up field, see PUx field Pull-up resistors, see I/O ports Pull-up/pull-down enable field, see PUx field Pulse width 7–0 field, see PWx field Pulse-width modulator 1, see PWM 1 Pulse-width modulator 2 i
Refresh cycle field, see REF field Refresh cycle, calculation of REF field values, 7-13 Refresh mode bit, see RM bit Refresh mode control register, see RMCR register Refresh rate field, see RRAx field REPEAT field, 15-5 Request to send pin bit, see RTS1 bit and RTS2 bit Reset exception, 9-4 instruction, 9-5 interrupt controller, 9-4 pin, see RESET pin status of RESET pin, 9-5 RESET pin description, 2-4 status during reset, 9-5 RESET signal delay for Dragonball and Dragonball EZ, 4-5 startup requirements, 9-
SB bit, 16-8 SCR register, 5-2 Screen starting address 31–1 field, see SSAx field SDRAM interface signals, 2-10 SDRAM, selecting multiplexing options, 7-5 to 7-6 SDRAM–to–MC68VZ328 connections, recommendations, 7-5 to 7-6 SELECT field NIPR1 register, 14-18 NIPR2 register, 14-28 Self-refresh mode, see LCD controller Self-refresh on bit, see REF_ON bit SELx field PBSEL register, 10-11 PCSEL register 10-14 PDSEL register, 10-19 PESEL register, 10-23 PFSEL register, 10-27 PGSEL register, 10-31 PJSEL register, 1
programming with ENABLE bit disabling writes, 13-14 setting before changing other bits, 13-12 registers control/status register, see SPICONT2 register data register, see SPIDATA2 register signals clock pin, see SPICLK2 pin introduction, 2-9 SPI master clock, see SPICLK2/PE2 pin SPI master receive data, see SPIRXD/PE1 pin SPI master transmit data, see SPITXD/PE0 pin timing diagrams, generic, 13-12, 19-32 using GPIO as chip-select, 13-13 SPI unit 2 interrupt pending bit, see SPI2 bit SPI unit 2 interrupt stat
UART clock I/O, see UCLK/DWE/PE3 pin Timer status register 1, see TSTAT1 register Timer status register 2, see TSTAT2 register TIN pin as a clock input, 12-3 transitions that trigger capture events, 12-3 TMR1 bit IPR register, 9-18 ISR register, 9-15 TMR2 bit IPR register, 9-18 ISR register, 9-14 TOUT pin, using to output a pulse on compare, 12-3 TOUT/TIN/PB6 pin description, 12-3 direction control, 12-3 signals, 2-8 TPRER1 register, 12-8 TPRER2 register, 12-8 TQFP mechanical drawing, 20-3 package dimension
signal nomenclature conventions, 14-1 signals UART 1 clear to send, see CTS1/PE7 pin UART 1 receive data, see RXD1/PE4 pin UART 1 request to send, see RTS1/PE6 pin UART 1 transmit data, see TXD1/PE5 pin UART 2 clear to send, see CTS2/PJ7 pin UART 2 receive data, see RXD2/PJ4 pin UART 2 request to send, see RTS2/PJ6 pin UART 2 transmitter data, see TXD2/PJ5 pin UART 1, compared to DragonBall EZ, 14-1 UBAUD1 register, 14-12 UBAUD2 register 14-22 UCLK direction bit, see UCLKDIR bit UCLK pin, connections, 14-4
