User manual
Page 40
Document No. 80-15151 Issue 6 HEBER LTD
Figure 3 - Schematic Sheet 3 - FPGA
ROM_ P12
D[0..15]2,4,6,7,9
FPGA [0. .6] 4
FPGA 5
FPGA 4
GND
FPGA 2
A21
SFX1_D0
ROM_ OE- 4
MPX_ OE 1 3
SFX2_VCK 5
X1
14.7456MHz
SFX1_D3
GND
SFX1_D[0..3]
N14
3K3*8 SIL
1
2
3
4
5
6
7
8
9
SFX1_D1
D11
VCC
D9
MPX_STR 13
SFX_CLK5,8
ROM_ P12 4
CS_ TTL- 9
A6
U6
FPGA
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
11
10
9
8
7
6
5
4
3
2
1
84
83
82
81
80
79
78
77
76
75
NC
I/O
I/O
I/O
I/O
I/O
GND
GND
I/O
I/O
I/O
I/O
I/O
VCC
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCC
VCC
MODE
I/O
I/O(CLK)
I/O
I/O
GND
GND
I/O
I/O
I/O
I/O
I/O
I/O
VCC
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCC
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
FPGA 2
R105
680R
CS_ O P- 6
A[0..23]
RA M_ OE- 4
SIZ02
FPGA 6
GND
VCC
MPX2_DATA_A 13
FPGA 0
A5
SFX2_D[0..3]
RA M_ WL- 4
VCC
FPGA 4
RA M_ WU- 4
DREQ2-2
R/W -2
A0
C35
100n
A1
SFX2_D3
R104
10M
CS2 -2
DREQ1-2
GND
GND
A3
56-15084 11r2
PLUTO 5 - FPGA
HEBER LTD.
Belvedere Mill
Chalfor d, Stroud, GL6 8NT
Tel: +44 (0) 1453 886000
Fax: +44 (0) 1 453 885 013
A3
313Tuesday , August 12, 2003
Title
Size Document Number Rev
Date: Sheet
of
VCC
FPGA 0
A23
CS0 -2
MPX_ CLK 13
GND
SFX2_D0
SFX1_VCK5
RESET10
SFX1_D[0..3]
SFX2_D1
GND
VCC
FPGA 3
VCC
GND
FPGA 1
VCC
SFX2_D2
FPGA [0. .6]
A7
GND
MPX1_DATA_A 13
3.68MHZ2
C37
33p
A2
SFX1_D2
C33
100n
A4
D8
D[0..15]
FPGA 5
FPGA 1
D15
A20
CS_ IP- 7
FPGA 3
CS1 -2
GND
CLKO UT2
EX TA L2
© HEBER LTD, 1996-2002
A19
D13
C36
100n
CS3 -2
GND
FPGA 6
A22
GND
SFX2_VCK
D14
C34
100n
MPX_STR_DATA_A 13
GND
D12
ROM_ P1 4
D10
A[0..23]2
VCC
C38
33p
VCC
VCC
CS_ TTL-
DSA CK0 -2,9
SFX2_D[0..3]
VCC