User manual
Page 38
Document No. 80-15151 Issue 6 HEBER LTD
Figure 1 - Schematic Sheet 1 - Root Sheet
LR[0..15]
PORTA [ 0. .7 ]
TXDB
© HEBER LTD, 1996-2002
CS3-
SHT 3 - FPGA
15084_3
CS_ O P-
CS_ IP-
R/W -
SIZ0
DSA CK0 -
EXTA L
3.68MHZ
CS0-
CS1-
CS2-
CS3-
CLKO UT
DREQ1-
DREQ2-
RA M_ WL-
RA M_ WU-
RAM_ OE-
ROM_ OE-
ROM_ P1
MPX_CLK
MPX_STR
MPX_OE
MPX1_DATA_A
MPX2_DATA_A
MPX_STR_DATA_A
SFX1_VCK
SFX_CLK
D[0..15]
A[0..23]
RESET
SFX1_D[0..3]
SFX2_D[0..3]
SFX2_VCK
ROM_ P12
CS_TTL-
FPGA [0. .6]
OP[0..63]
RA M_ CS -
DSA CK1 -
MPX_REF1
VREF
A[0..23]
PO RTA [ 0. .7 ]
RXDA
SHT 6 - OPEN DRA IN OUTPUTS
15084_6
RESET-
CS_OP-
D[0..15]
OP[0..63]
A[0..23]
SEL[0..2]
RESET-
NMI-
PB5
SHT 1 2 - LA MP ROW SOURCES
15084_C
CLK_12V
STR_12V
OE_12V
MPX1_A_12V
MPX1_B_12V
MPX1_C_12V
MPX1_D_12V
LR[0..15]
BERR-
SFX1_D[0..3]
SHT 7 - INPUTS/DIL SW
15084_7
D[0..15]
CS_IP-
IP[0..3 1]
SEL[0..2]
CLKO UT
DS-
EXTA L
MPX_REF1
SFX_CLK
CS_ IP-
RESET
TXDA
SFX_CLK
MPX2_DA TA_ A
PB6
RTSB-
DREQ1-
SHT 1 3 - LED S EG DRIVES
15084_D
MPX_CLK
MPX_STR
MPX_OE
MPX1_DATA_A
CLK_12V
STR_12V
OE_12V
MPX1_A_12V
STR_A_12V SEG[0..1 5]
MPX1_B_12V
MPX1_C_12V
MPX1_D_12V
MPX_STR_DATA_A
MPX2_DATA_A
SHT 1 1 - COL/DIG SINKS
15084_B
CLK_12V
STR_12V
OE_12V
STR_A_12V
SEG[0..15]
LC[0..15]
MPX_ REF1
MPX_ REF2
CS_OP-
AS-
VREF
FC3
TGA TE2-
D[0 .. 15]
RTSA -
MPX_REF2
SFX2_VCK
MPX_CLK
CS3 -
MPX_STR
RTSA -
SIZ1
RXDB
DREQ2-
RESET
SIZ0
TGA TE2-
PORTA [ 0. .7]
AS-
D[0..15]
PB5
A[0..23]
TOUT2
3.68MHZ
MPX_OE
TGA TE1-
CS_TTL-
PB0
PO P4
MPX_STR_DATA_A
TXDA
PORTA [ 0. .7 ]
CTSA -
DSA CK0 -
SHT 2 - MC68340 CPU
15084_2
R/W-
SIZ0
DSA CK0-
EXTA L
3.68MHZ
CS0-
CS1-
CS2-
CS3-
CLKO UT
DREQ1-
DREQ2-
D[0..15]
A[0..23]
METER_SENSE
NMI-
CTSA -
RTSA -
CTSB-
RTSB-
PO RTA [0 . .7 ]
SEL[0..2]
AS-
DS-
DSA CK1-
SIZ1
FC3
PB5
PB6
RXDA
RXDB
TXDA
TXDB
TGA TE1-
TGA TE2-
TOUT1
TOUT2
PO P4
PO P6
HA LT-
BERR-
RESET-
PB0
PB6
METER_SENSE
CS0-
MPX1_DA TA_ A
D[0 ..15]
SIZ1
SHT 4 - EPRO M/RA M
15084_4
D[0..15]
A[0..23]RAM_ WL-
RAM_ WU-
RAM_ OE-
ROM_ OE-
ROM_ P1
RAM_ CS-
ROM_ P12
FPGA [0. .6 ]
SHT 1 0 - RESET/ BATT/RS232/I2 C
15084_A
VREF
RAM_ CS-
RESET
CTSA -
RTSA -
CTSB-
RTSB-
RXDA
TXDA
RXDB
TXDB
RESET-
PB0
PO RTA [0 . .7 ]
SEL[0..2]
SHT 5 - SOUND
15084_5
SFX_CLK
SFX1_VCK
SFX1_D[0..3]
TOUT1
PO P6
PO P4
TOUT2
SFX2_D[0..3]
SFX2_VCK
PO RTA [ 0. .7 ]
R/W -
D[0 ..15]
CS_ O P-
CTSA -
CS1-
DSA CK1 -
A[0..23]
CS_IP-
RESET-
RESET-
R/W -
METER_SENSE
A[0..23]
CTSB-
MPX_REF2
IP[0..3 1]
FPGA [0..6]
RAM_ CS-
PO P6
TGA TE1-
PO RTA [0 . .7 ]
HA LT-
LC[0..15]
DSA CK0 -
SHT 9 - CONNECTORS
15084_9
OP[0..63]
RESET-
TXDA
CTSA -
RTSA -
IP[0. .3 1]
AS-
DS-
R/W -
DSA CK0 -
DSA CK1 -
SIZ0
SIZ1
CS3 -
CLKO UT
RXDA
TGA TE1-
TGA TE2-
PB 5
PB 6
LC[0..15]
MPX1_B_12V
MPX1_D_12V
MPX1_C_12V
LR[0..15]
BERR-
HA LT-
A[0..23]
D[0 ..15]
PO RT A [ 0 . . 7 ]
CS_ TTL-
RXDA
NMI-
SEG[0..15]
SHT 8 - +5V /CURRENT SENSE
15084_8
METER_SENSE
NMI-
VREF
SFX_CLK
MPX_REF2
MPX_REF1
PO RTA [0 . .7 ]
HA LT-
SIZ0
CS2-
56-15084 11r2
PLUTO 5 - ROOT SHEET
HEBER LTD.
Belvedere Mill
Chalford, Stroud
Glo ucestershire GL6 8NT
Tel: 0453 886000 Fax: 0453 885013
A3
113Monday, August 11 , 2003
Title
Size Document Number Rev
Date: Sheet
of
CS_TTL-
DS-
CLKO UT
D[0..15]
SFX1_VCK
BERR-
TOUT1
SFX2_D[0..3]