User manual

Page 18
Document No. 80-15151 Issue 6 HEBER LTD
5.17 Sound Generation
The sound generation circuits are shown on Schematic Sheet 5 - Sound.
U8 and (optionally) U39 are the source of Sound Channel 1 & 2 respectively with the audio output
being pin 10, Aout. These OKI MSM6585 devices are 4 bit ADPCM D-A converters capable of running
at sample rates of 4KHz, 8KHz, 16KHz or 32KHz. This rate is selected by software by setting levels on
the S1 and S2 pins. On Channel 1 (U8) these pins are controlled by the OP4 and OP6 lines from the
MC68340 Serial Module. On Channel 2 (U39) these pins are controlled by the PORTA6 and PORTA7
lines from the MC68340 SIM40 Module.
The VCK- output from the MSM6585 is a square wave at the sampling frequency selected by S1 and
S2. The MSM6585 reads the 4 bit sample immediately after the rising edge of VCK-.
The VCK- from the MSM6585 is connected to the FPGA where it is divided by 2 to produce a DMA
Request signal to the processor. Sound data is transferred, a byte at a time (1 byte = 2 * 4 bit sound
samples), to the appropriate register within the FPGA by the DMA Module if a sound is being played.
The FPGA in turn presents alternately the high and low nibble to the MSM6585 OKI chip.
The sound channel requests a byte of data (via the FPGA) at half the sound sample rate. E.g., if the
MSM6585 has been set to run at 16KHz sample rate, the FPGA will issue DMA requests at 8KHz.
These requests are issued continuously to the DMA Module, but in times of silence, the DMA
channels are inactive and therefore no new data is transferred into the FPGA sound register. In this
case, the user must ensure that the last data written to the FPGA sound register before a period of
silence is 0x80. This will ensure that, during a silent period, the MSM6585 is being continuously fed a
repeated sequence of alternate 0x8 and 0x0 nibbles. This keeps the ADPCM converter in its quiescent
state. If the sound data is generated using the Heber Sound Solutions software, the last byte of the
data is always 0x80, so this condition will automatically be satisfied.
Sound Channel 1 (U8) is fitted as standard and uses DMA Channel 1. Sound Channel 2 (U39) is
optional and uses DMA Channel 2.
The RESET pin of each channel is under individual software control. Pin PORTA0 drives SFX
Channel #1 RESET. Pin PORTA1 drives SFX Channel #2 RESET. After Power –Up, these pins will
default to being inputs and therefore the Resistor network N11 will pull them High, holding both Sound
Channels in a RESET state. Before the Sound Channels can be used, these two pins must be set as
outputs by the SIM40.
5.18 Stereo Amplifier and Volume Controls
The Stereo Amplifier is shown on Schematic Sheet 5 - Sound.
U32 is a Philips TDA7057AQ Stereo Audio Amplifier with independent DC volume controls. Note that
the loudspeaker outputs, on Connector P10, are bridge driven so neither of the loudspeaker wires may
be connected to Gnd.
The DC volume controls of the TDA7057 work over the range 0.4V(min) to 1.2V (Max). The variable
duty cycle outputs on pins TOUT1/2 from the two timers in the MC68340 Timer Module are integrated
by the combination of two 3K3 resistors and a 1µF capacitor (R108, R109, C45 on Channel 1: R110,
R113, C46 on Channel 2) to provide the control voltage needed. The control voltage is given by the
formula 2.5*{duty cycle} where “duty cycle” is the proportion of the time that the TOUT Pin is HIGH.
Normally, Sound Channel 1 (U8, DMA Channel 1) feeds Amplifier Section 1 (volume control - Timer
Channel 1) driving LS1. Sound Channel 2 (U39, DMA Channel 2) feeds Amplifier Section 2 (volume
control – Timer Channel 2) driving LS2.
A pin on the Loudspeaker Connector, P10, pin 3, which allows the output signal from Amplifier
Channel 1 to be fed back into the input of Amplifier Channel 2. This allows various alternative modes