User manual

Page 17
Document No. 80-15151 Issue 6 HEBER LTD
5.16 Multiplexed Lamp Current Sense
A facility is provided to allow the processor to check the 256/128 possible lamp positions of MPX1 to
determine:
a. Is a light bulb present?
b. Is there a short circuit in this position?
This facility is intended to be run at power up and, perhaps, as a production test. The facility cannot be
used during normal operation of the machine.
A resistance of approximately 24mΩ is implemented, as a copper track on the PCB, between common
source connection of all the Lamp Column/LED Digit sinks, Q35-50 and Gnd (see Schematic Sheet 11
- Lamp Column/LED Digit Drives). The voltage across this resistor is compared against 2 thresholds
formed by resistor chain R124, R125 and R126 by comparators U16C and U16D (see Schematic
Sheet 8 - Power Supply). These thresholds correspond to nominal currents of about 375mA and 4.8A.
The outputs of the 2 comparators, U16C and U16D are connected to processor lines PORTA6 and
PORTA7. The current sensing comparators may be disabled by SFX_CLK being enabled. When
SFX_CLK, a 640kHz clock, is enabled by setting a bit in the FPGA (see FPGA User Manual), the “+”
inputs of the 2 comparators are pulled up to about +5V by D21/C9/C10 which forces the comparator
outputs (which are open collector) OFF. In this state the lines PORTA6 and PORTA7 are free to be
used as outputs driving the S1 & S2 pins of SFX Channel #2 or as required by any card fitted to the
I/O Expansion Connector, P14. When the SFX-CLK is turned OFF (and forced low), any voltage on
C9/10 is discharged by R127, and the current sensing circuit is enabled.
With no current through the Column/Digit Sinks, both outputs PORTA6/7 will be LOW because V+ < V-
on the comparators. When the current through the 24mΩ resistor exceeds a nominal 375mA, PORTA6
will go high. When the current exceeds a nominal 4.8A, PORTA7 will also go high.
The sequence of operation to test a lamp is as follows:
• Turn off SFX_CLK in FPGA to enable circuit.
• Turn off all Row/Digit drives on MPX1.
• Ensure PORTA6 and PORTA7 both read 0
• Turn on lamp to be tested on multiplex by writing appropriate data to FPGA.
• Start a 1mS timer.
• Loop watching lines PORTA6 and PORTA7.
• If PORTA7 line goes high, there is a short circuit in this position, so immediately disable the
multiplex drives by turning off Multiplex OE line in the FPGA.
• If PORTA6 line goes high but not PORTA7, then there is a light bulb connected and apparently
working.
• If 1mS timer times out without either line going high, then either no bulb present or it is open
circuit.
• Record result and go on to next bulb.
• When complete, act as required on results. Re-enable SFX-CLK to allow Sound Channels to work.