User manual

Page 14
Document No. 80-15151 Issue 6 HEBER LTD
5.10 AUX Outputs, AUX0-7
8 auxiliary TTL level open drain outputs are provided by U30 (see Schematic Sheet 9 - IO
Connectors). U30 is a TPIC6B259 which functions exactly the same as the TPIC6259 devices used to
drive OP0-63, but with a lower drive capability (see data sheet “tpic6b259.pdf”).
They are memory mapped as the least significant bit of a block of 8 bytes of address space at an
address determined by the FPGA fitted to the board. See the appropriate FPGA User Manual for
details.
They are open drain outputs fitted with 1K pull-up resistors to Vcc.
AUX0-5 are routed to connector P12 “AUX OUTPUTS”.
AUX6-7 are routed to Connector P13 “I
2
C”.
5.11 Inputs, IP0-31
External inputs are catered for by 32 input lines, IP0-31 (see Schematic Sheet 7 - Inputs). Like the
Open Drain outputs these are memory mapped as the least significant byte of a block of 4 words of
address space.
Each input is provided with a 3K3 pull-up resistor to Vcc (+5V) and feeds into a 74HC family device
(rather than 74HCT). This give the inputs a low level threshold of <1.5V and a high threshold of
>3.5V. The 47K resistor in series with the input protects the 74HC253 devices from noise spikes or
high voltages on the inputs.
The 1.5V low threshold allows the inputs to be safely driven as a multiplexed array with a diode in
series with each switch with the strobes generated using a number of the Open Drain Outputs, OP0-
63, described above.
The 32 inputs are mapped as shown in the following table. The top 4 bits of each word are read as
“1”s and bits 8 to 11 contain the DIL Switch Settings (as described in the next section). The base
address is defined by the FPGA.
Table 11. Mapping of Inputs IP0-31
D15-12 D11-8 D7 D6 D5 D4 D3 D2 D1 D0
Base+6
0xF
DIL
SW
IP31 IP30 IP29 IP28 IP27 IP26 IP25 IP24
Base+4
0xF
IP23 IP22 IP21 IP20 IP19 IP18 IP17 IP16
Base+2
0xF
IP15 IP14 IP13 IP12 IP11 IP10 1P9 IP8
Base
0xF
IP7 IP6 IP5 IP4 IP3 IP2 IP1 IP0