User manual

Page 10
Document No. 80-15151 Issue 6 HEBER LTD
5.5 FPGA
The Pluto 5 Controller is fitted with an 84 lead PLCC socket, position U6, into which is plugged an
FPGA. The standard FPGA type used is an Actel A40MX04-PL84. The purpose of fitting an FPGA to
the system is twofold. First, to allow the Pluto 5 Controller to be uniquely configured for each user of
the system to give commercial and software security (see the FPGA SECURITY MANUAL).
Secondly, it allows particular advanced features, for example, the EPROM Autoselect and Multiplex
dimming, to be economically implemented.
The following main functions are carried out by the FPGA:
• Control automatic EPROM mode selection
• Generate control signals for on-board EPROM and RAM
• Generate control signals for Memory Expansion Connector P15.
• Generate DMA requests and multiplex data for Sound Channels 1 & 2.
• Control and drive of data to Multiplex Arrays, both on-board MPX1 and expansion MPX2.
• Provide various levels of Software Security.
• Form an oscillator with 14.75MHz resonator:
• Generate Main Clock, EXTAL for MC68340 Processor @32.768kHz.
• Generate clock for MC68340 Serial Module @3.6864MHz.
• Generate clock for OKI MSM6585 devices, U8/39 @640KHz.
5.6 EPROM Sockets / EPROM Autoselect Feature
The 2 EPROM positions, U1 and U2, are configured such that 4 possible configurations of programme
memory are possible (assuming no external memory expansion via P15):
Table 5. Possible EPROM Configurations
U1 U2 Mode Configuration Total Size Addresses
scrambled
27C040 omit 8 bit 512k*8 512Kbyte no
27C040 27C040 16 bit 512K*16 1Mbyte yes
27C801 omit 8 bit 1024k*8 1Mbyte no
27C801 27C801 16 bit 1024k*16 2Mbyte yes
It is not necessary to change any links on the board in order to switch between different memory
configurations. All relevant switching is carried out within the FPGA, which contains an “EPROM
Autoselect” feature. After Power-up, during the reset period, the FPGA reads the top byte address of
U1. Data contained in this byte defines the memory configuration required and the FPGA
sets up the
control lines to the EPROM sockets accordingly, so that, at the end of reset, the
processor is able to read the EPROM(s) correctly.
Thus, after the final linked EPROM software module has been created, prior to being blown into
EPROM, the top location of the memory must be overwritten with suitable data to signify the EPROM
configuration that will be used.
This is the feature referred to as EPROM Autoselect. A full operational description of this feature is
given in the User manual for the FPGA in use on the Pluto 5 Controller Board.
As with the Pluto 1 System, in order to facilitate the option to use either 1 or 2 EPROMs, i.e. run in 8
bit or 16 bit mode, it is necessary to have some scrambling of the address lines to the EPROMs when
operating in 16 bit mode. Therefore, prior to blowing 16 bit EPROMs, the data must be re-arranged to
compensate. A software utility is provided with the Pluto 5 Development Kit to carry this out.