User manual

Page 6
Document No. 80-15151 Issue 6 HEBER LTD
5.4.1 CPU32 Processor Module
The CPU32 is a processing core which is basically 68000 code compatible but with a number of
enhancements. For full details of operation please refer to both the Motorola MC68340 User Manual
and the Motorola M68000 Family Programmers Reference Manual [see Adobe Acrobat File
68kprm.pdf].
All modern 68000 Compilers and Assemblers have various options for the target CPU. When
generating code for the Pluto System, the CPU32 option should be used.
If the Compiler/Assembler is old it is possible that it may not have a CPU32 option. In this case, the
Compiler (if used) should be run with the 68000 option set. The assembler may be run in 68020 mode
which will allow the use of the MOVES command which is required during initialisation to set up the
Module Base Address Register (MBAR) in the MC68340. Care must be taken not to write code that
calls any other 68020 instructions that may not be implemented on the CPU32.
The Pluto 5 Development Kit includes a suitable C Compiler and Assembler.
5.4.2 SIM40 System Integration Module
This module controls various aspects of the operation of the processor, such as configuration, clock,
external bus, etc.
When used in the Pluto System, the main considerations in the use of this module are:
5.4.2.1 Module Base Address Register
Set the Module Base Address Register, MBAR, to a suitable address during initialisation.
This sets the base address of all the internal module registers. In the example code it is set
in Module “except.asm” to value 0xffff f000. There is nothing magic about this value, but
obviously it must be set to an address that is clear of any other devices in the processor
memory map. This register must be set before any other module initialisation is attempted.
5.4.2.2 Chip Selects
Set-up the 4 Chip Select outputs, CS0- to CS3-. The Pluto 5 System allocates these as
follows:
CS0 - is used to map the system programme memory. This consists of any EPROM fitted to
the on-board EPROM sockets, U1 and U2 plus any extra EPROM or FLASH devices fitted to
the Memory Expansion Connector, P14. Exact mapping, within the area defined by CS0-, is
carried out be the system FPGA.
CS1 - is used to map the on-board, battery backed RAM and, if fitted, any external RAM on
a memory card on connector P15.
CS2 - is used to map both the internal registers of the FPGA and the on-board I/O,
CS3 - is normally spare and is available on the I/O expansion connector, P14. Its main use is
for the selection of the optional add-on CGA/VGA Video Card.
After hardware reset, CS0- will be asserted for memory accesses anywhere in the memory
map which allows the processor to boot. However, the chip selects must be programmed
immediately after Reset and prior to any function or subroutine calls, because until they are,
CS1- will not be active and therefore it will not be possible for the processor to access RAM.
Example code for setting up the 4 pairs of Chip Select Base and Mask registers is given in
Module except.asm
5.4.2.3 Periodic Interrupt Timer.
The “sim40_m.c” Module in the Sample Software sets this timer to provide a high priority
1mS interrupt which is normally used by the software to provide basic system timing. This
function is controlled by the PICR and the PITR.