User manual

Page 5
Document No. 80-15151 Issue 6 HEBER LTD
processor the NMI in advance of the RESET is to avoid the risk of an incomplete RAM write operation
occurring if the RESET were to be asynchronously asserted while such an operation was being
carried out.
The time available between the assertion of NMI and the assertion of RESET will depend on the rate
of fall of the +12V line, which will obviously be dependent upon the power supply and the loading on
the +12V, but will typically be several milliseconds.
5.3 Battery Backup
A backup battery, BT1, is provided (see - Schematic Sheet 10 - Reset/Battery/RS232) to allow the two
RAMs U3 and U4 to retain data while the board is powered down and to keep the optional Real Time
Clock chip, U40, running.
BT1 is a two cell rechargeable NiMH (Nickel Metal Hydride) battery, capacity 70mA/hr. The circuit
comprising BT1, Q2, R43 and R132 provides the battery trickle charge and switchover of the secured
power supply rail, Vbatt.
While Vcc is at 5V, current flows through the base-emitter junction of Q2 through R43 into the battery.
On charge, the voltage on BT1 will be about 2.6V so the current through R43 will be (5-V
BE
-2.6)/3300,
about 0.5mA. Thus Q2 will be turned ON and Vbatt will be a V
CEsat
below Vcc. Current will therefore
also flow through R132 into Vbatt, (5-V
CEsat
-2.6)/3300, about 0.7mA. Total trickle charge current is
therefore 0.5 + 0.7 = 1.2mA. The specification of the cells calls for a trickle charge of between .01C
and .03C. C is 70mA, so the acceptable range is between .7mA and 2.1mA.
When power is removed, Vcc collapses to ground. The base-emitter junction of Q2 is now reverse
biased and therefore no current flows through R43 and Q2 is OFF. Vbatt is now connected to the
positive end of BT1 via R132. The discharge current into the RAMs and RTC should not exceed 40µA,
which will result in a voltage drop in R132 of less than 0.15V. This gives a worst case battery life in
excess of two months, and in practice much higher.
When on battery backup it is vital that the RAMs are placed in the standby state by ensuring that the
CS- line is high. Q1 and R42 achieve this. When the RESET- line goes low, which may occur either as
a result of a Reset occurring or Vcc collapsing, Q1 turns OFF causing the CS- lines to the RAMs to be
pulled to Vbatt by R42.
5.4 The MC68340 Processor
Full details of the operation of the processor is given in the Motorola MC68340 User Manual [see
Adobe Acrobat File 68340um.pdf, plus Addenda files 68340um_ad.pdf and 68340um_ad2.pdf]
The MC68340 contains the following functional blocks: