Specifications
10
Downloading Procedures
A Widows terminal settings file is also included on the disk. Execute the following steps to download a program:
1. Start Windows.
2. Choose
RUN
from the
FILE
menu.
3. Type
A:\MC68340.TRM
to start the Windows Terminal program.
4. Type
LO and press <ENTER>.
5. Choose
Send Text File from the Transfers menu.
6. Select
HARDWARE.ABS from A:\HARDWARE directory.
7. When download has completed, hit
<ENTER> twice.
Once the program has been downloaded, use the RM command to initialize the MC68340 registers. Set PC to $4000,
USP to $8000 and SSP to $10000.
Programmed I/O Test
In Programmed I/O, 5 different tests are conducted that make accesses to FIFOs. These five tests are:
1. 8 Bit Accesses to FIFO A
2. 8 Bit Accesses to FIFO B
3. 16 Bit Accesses to FIFOs
4. 8 Bit Writes and 16 Bit Reads
5. 16 Bit Writes and 8 Bit Reads
Programmed I/O tests 1 and 2 write all possible values (0-255) to both the FIFOs using the upper byte lane and the
lower byte lane. Test 3 makes 16-bit accesses to the FIFOs by writing specific values which test the address and data
lines (stuck-0,stuck-1,stuck-together). Tests 4 and 5 write the exact same values as in test 3, but 8 bit write and 16 bit
read is performed in test 4 while the opposite is performed in test 5. These tests make sure that the FIFOs can be
accessed properly and also test the hardware interface such as the address lines, data lines and bus operation signals.
Interrupt Driven I/O Test
By performing the Interrupt Driven I/O we are testing to make sure that the TNT4882 can assert its interrupt line and
that it gets acknowledged properly. Before we do any I/O we do a sanity check to make sure that the interrupt handler
has been loaded properly. The program reads the contents of memory location $06C (IRQN3) and compares it with
the address of the interrupt handler. If a mismatch occurs, the interrupt handler is not getting loaded properly, or the
vector table is being altered which results in the loss of the handler address. Once the handler has been loaded properly,
NFF bit of IMR3 is enabled. If FIFOs have room for a byte, an interrupt will occur. After writing to the FIFOs we
enable the NEF bit of IMR3. An interrupt will occur if FIFOs contain bytes that need to be transferred to memory.
If the interrupts do not get acknowledged, chances are that the interrupt line is not connected properly. If an unexpected
interrupt occurs, then your system may have deleted the address of the new handler from the exception vector table.
DMA I/O Test
DMA I/O tests the functionality of the DMA Channel and its associated interface logic. For example, when a DMA
read is performed, data is transferred from memory (read from memory) to the TNT4882. If data transfers do not take
place, chances are that WRN signal is not asserting during the DMA read cycle. Similarly, during a DMA write cycle,
RDN should be asserted because data is transferred from FIFOs to memory.