User`s guide

Table 6 (Cont.)
MC68306 Signal List
POD PIN LA BIT PGA PIN QFP PIN 68306 LABEL BUS LABEL ALT BUS SIG LABEL
P4
1
37 0 L8 128 A16 ADDR
P4
1
35 1 J8 126 A17 ADDR
P4
1
33 2 K8 125 A18 ADDR
P4
1
31 3 L9 124 A19 ADDR
P4
1
29 4 K2 19 A20 ADDR CS ~CS4
P4
1
27 5 L1 18 A21 ADDR CS ~CS5
P4
1
25 6 M2 16 A22 ADDR CS ~CS6
P4
1
23 7 L2 15 A23 ADDR CS ~CS7
P4
1
218F437R/~WSTAT R/~W
P4
1,2
199F235~LDS STAT SIZE ~LDS
P4
1,2
17 10 F1 36 ~UDS STAT SIZE ~UDS
P4 15 11 B2 48 ~RESET STAT ~RESET
P4
1
13 12 B3 52 FC0 STAT FC FC0
P4
1
11 13 A2 51 FC1 STAT FC FC1
P4
1
9 14 B1 49 FC2 STAT FC FC2
P4
1,5
7 15 E2 39 ~BGACK STAT ~BGACK
P4
1
3 Clock 1 F3 38 ~AS ~AS
(M clock)
Notation:
~ Signal is active low.
1 Signal is required for inverse assembly.
2 This is a delayed version of the signal (10 nsec) for state analysis.
5. Although ~BGACK is available on both preprocessor connectors P2 and P4, the individual signal label is assigned to P4
in the logic analyzer Format menu because this pod connection is required for inverse assembly. The P2 version of
~BGACK is used as one of the bits for BUS LABEL "BUS".
Preprocessor Interface Hardware Reference
Signal-to-Connector Mapping
3–10 MC68306 Preprocessor