User`s guide

Table 6 (Cont.)
MC68306 Signal List
POD PIN LA BIT PGA PIN QFP PIN 68306 LABEL BUS LABEL ALT BUS SIG LABEL
P3
1,2
190F136~UDSADDR
P3
1
18 1 M3 14 A1 ADDR
P3
1
172L412A2 ADDR
P3
1
16 3 K4 11 A3 ADDR
P3
1
15 4 M4 10 A4 ADDR
P3
1
14 5 K5 9 A5 ADDR
P3
1
13 6 J5 8 A6 ADDR
P3
1
12 7 L5 6 A7 ADDR
P3
1
11 8 K6 5 A8 ADDR
P3
1
10 9 J6 4 A9 ADDR
P3
1
9 10 M6 3 A10 ADDR
P3
1
8 11 L6 2 A11 ADDR
P3
1
7 12 L7 132 A12 ADDR
P3
1
6 13 M7 131 A13 ADDR
P3
1
5 14 J7 130 A14 ADDR
P3
1
4 15 K7 129 A15 ADDR
P3 3 Clock 1 D2 45 CLKOUT CLKOUT
(L clock)
Notation:
~ Signal is active low.
1 Signal is required for inverse assembly.
2 This is a delayed version of the signal (10 nsec) for state analysis.
Preprocessor Interface Hardware Reference
Signal-to-Connector Mapping
MC68306 Preprocessor 3–9