User`s guide

Table 6 (Cont.)
MC68306 Signal List
POD PIN LA BIT PGA PIN QFP PIN 68306 LABEL BUS LABEL ALT BUS SIG LABEL
P2 19 0 M9 123 AMODE STAT_B AMODE
P2 18 1 C3 53 ~DTACK STAT_B ~DTACK
P2 17 2 G4 31 ~OE STAT_B ~OE
P2 16 3 G1 32 ~LW STAT_B ~LW
P2 15 4 G2 33 ~UW STAT_B ~UW
P2 14 5 C1 47 ~HALT STAT_B ~HALT
P2 13 6 A3 54 ~BERR STAT_B ~BERR
P2 12 7 F3 38 ~AS STAT_B ~AS
P2 11 8 J1 24 ~CS0 CS ~CS0
P2 10 9 J4 23 ~CS1 CS ~CS1
P2 9 10 K1 21 ~CS2 CS ~CS2
P2 8 11 K3 20 ~CS3 CS ~CS3
P2
5
7 12 E2 39 ~BGACK BUS
P2 6 13 E4 41 ~BG BUS ~BG
P2 5 14 E3 42 ~BR BUS ~BR
P2 4 15 D2 45 CLKOUT CLKOUT
P2 3 Clock 1 L10 118 TCK TCK
(K clock)
Notation:
~ Signal is active low.
5. Although ~BGACK is available on both preprocessor connectors P2 and P4, the individual signal label is assigned to P4
in the logic analyzer Format menu because this pod connection is required for inverse assembly. The P2 version of
~BGACK is used as one of the bits for BUS LABEL "BUS".
Preprocessor Interface Hardware Reference
Signal-to-Connector Mapping
3–8 MC68306 Preprocessor