User`s guide

Table 6
MC68306 Signal List
POD PIN LA BIT PGA PIN QFP PIN 68306 LABEL BUS LABEL ALT BUS SIG LABEL
P1
1
19 0 D8 74 D0 DATA
P1
1
18 1 B8 72 D1 DATA
P1
1
17 2 C7 71 D2 DATA
P1
1
16 3 D7 70 D3 DATA
P1
1
15 4 A7 69 D4 DATA
P1
1
14 5 B7 68 D5 DATA
P1
1
13 6 B6 66 D6 DATA
P1
1
12 7 A6 65 D7 DATA
P1
1
11 8 D6 64 D8 DATA
P1
1
10 9 C6 63 D9 DATA
P1
1
9 10 B5 62 D10 DATA
P1
1
8 11 D5 60 D11 DATA
P1
1
7 12 C5 59 D12 DATA
P1
1
6 13 B4 58 D13 DATA
P1
1
5 14 A4 57 D14 DATA
P1
1
4 15 D4 56 D15 DATA
P1 3 Clock 1 C3 53 ~DTACK ~DTACK
(J clock)
Notation:
~ Signal is active low.
1 Signal is required for inverse assembly.
Preprocessor Interface Hardware Reference
Signal-to-Connector Mapping
MC68306 Preprocessor 3–7